Trench power MOSFET with reduced on-resistance

• US 8,362,550 B2
• Filed: 06/13/2011
• Issued: 01/29/2013
• Est. Priority Date: 01/20/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Rexer, Christopher L., Sodhi, Ritu
• Primary Examiner(s): Dang, Trung Q
• Application Number:
  US13/158,927
• Publication Number:
  US 20120187474A1
• Time in Patent Office: 596 Days
• Field of Search: 257/330, 257/E29.262, 257/E21.41, 438/270
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a drift region, a well region extending above the drift region, an active trench including sidewalls and a bottom, the active trench extending through the well region and into the drift region and having at least portions of its sidewalls and bottom lined with dielectric material. The device further includes a shield disposed within the active trench and separated from the sidewalls of the active trench by the dielectric material, a gate disposed within the active trench above the first shield and separated therefrom by inter-electrode dielectric material, and source regions formed in the well region adjacent the active trench. The gate is separated from the sidewalls of the active trench by the dielectric material. The shield and the gate are made of materials having different work functions.

Claims

1. A semiconductor device comprising:

a drift region of a first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

an active trench comprising sidewalls and a bottom, the active trench extending through the well region and into the drift region and having at least portions of its sidewalls and bottom lined with dielectric material;

a first shield disposed within the active trench and separated from the sidewalls of the active trench by the dielectric material;

a gate disposed within the active trench above the first shield and separated therefrom by inter-electrode dielectric material, the gate being separated from the sidewalls of the active trench by the dielectric material; and

source regions having the first conductivity type formed in the well region adjacent the active trench, wherein the first shield and the gate are made of materials having different work functions.

2. The semiconductor device of claim 1 wherein the first shield comprises an N-type polysilicon and the gate comprises P-type polysilicon.

3. The semiconductor device of claim 2 wherein the drift region is an epitaxially grown P-type material.

4. The semiconductor device of claim 2 wherein an N-type polysilicon material in the first shield provides an accumulation layer along the trench adjacent to the drift region.

5. The semiconductor device of claim 1 wherein the first shield comprises an N-type polysilicon and the gate comprises a metal.

6. The semiconductor device of claim 1 wherein the first shield comprises P-type polysilicon and the gate comprises N-type polysilicon.

7. The semiconductor device of claim 6 wherein the drift region is an epitaxially grown N-type material.

8. The semiconductor device of claim 6 wherein the P-type polysilicon in the first shield provides an accumulation layer along the trench adjacent to the drift region.

9. The semiconductor device of claim 1 wherein the drift region is formed over a substrate and the active trench extends into the substrate.

10. The semiconductor device of claim 1 wherein the first shield and the gate are configured to be electrically coupled to substantially the same potential.

11. The semiconductor device of claim 1 wherein:

the first shield comprises an N-type polysilicon;

the gate comprises P-type polysilicon;

the active trench further comprises a second shield; and

the second shield comprises an N-type polysilicon material disposed below the first shield.

12. The semiconductor device of claim 1 wherein:

the first shield comprises an N-type polysilicon;

the gate comprises P-type polysilicon; and

the active trench further comprises a plurality of second shields disposed below the first shield, the plurality of second shields being stacked below the first shield.

13. The semiconductor device of claim 1 wherein the shield inside the active trench forms a secondary gate electrode that is configured to be electrically biased to a desired potential.

14. The semiconductor device of claim 13 wherein the gate and the secondary gate electrode are configured to be independently electrically biased.

15. The semiconductor device of claim 14 wherein the secondary gate electrode is configured to be biased at a constant potential at approximately a threshold voltage of the semiconductor device.

16. The semiconductor device of claim 14 wherein the secondary gate electrode is configured to be biased at a potential that is greater than a potential applied to the source regions.

17. The semiconductor device of claim 14 wherein the secondary gate electrode is configured to be coupled to a potential at approximately a threshold voltage of the semiconductor device before a switching event.

18. The semiconductor device of claim 13 wherein the active trench further comprises a third conductive layer disposed under the secondary gate electrode, the third conductive layer being isolated from the secondary gate electrode and the trench sidewalls and bottom by dielectric material, the third conductive layer forming a shield electrode that is configured to be electrically biased to a desired potential.

19. A semiconductor device comprising:

a drift region of an epitaxially grown P-type conductivity material;

a well region extending above the drift region and having an n-type conductivity material;

an active trench comprising sidewalls and a bottom, the active trench extending through the well region and into the drift region, the active trench having at least portions of its sidewalls and bottom lined with dielectric material;

a first shield disposed within the active trench and separated from the sidewalls of the active trench by the dielectric material, the first shield comprising an N-type polysilicon material;

a gate disposed within the active trench above the first shield and separated therefrom by inter-electrode dielectric material, the gate being separated from the sidewalls of the active trench by the dielectric material, the gate comprises a material different than the first shield material; and

source regions having a P-type conductivity formed in the well region adjacent the active trench.

20. The semiconductor device of claim 19 wherein the drift region is formed over a substrate and the active trench extends into the substrate.

21. The semiconductor device of claim 19 wherein the gate comprises a metal material.

22. The semiconductor device of claim 19 wherein the N-type polysilicon material in the first shield provides an accumulation layer along the trench adjacent to the drift region.

23. The semiconductor device of claim 19 wherein the inter-electrode dielectric material has a thickness that is thicker than the dielectric material.

24. A method of forming a semiconductor device comprising:

forming a drift region of a first conductivity type;

forming an active trench extending through a well region and into the drift region, the active trench comprising sidewalls and a bottom;

lining portions of sidewalls of the active trench and a bottom of the active trench with a dielectric material;

forming a shield comprising an N-type polysilicon material within the active trench and separated from the sidewalls of the active trench by the dielectric material;

forming an inter-electrode dielectric material over the shield in the active trench;

forming a well region extending above the drift region, the well region having a second conductivity type opposite the first conductivity type;

forming a gate within the active trench above the shield and separated therefrom by the inter-electrode dielectric material, the gate being separated from the sidewalls of the active trench by the dielectric material, the gate comprises a material different than the shield material; and

forming source regions in the well region adjacent the active trench, the source regions having the first conductivity type.

25. The method of claim 24 wherein the drift region is formed over a substrate and the active trench is formed to extend into the substrate.

26. The method of claim 24 wherein forming the gate comprises forming a P-type polysilicon material in the active trench.

27. The method of claim 24 wherein forming the shield comprising an N-type polysilicon material provides an accumulation layer along the trench adjacent to the drift region.

28. The method of claim 24 wherein forming an inter-electrode dielectric material further comprises depositing the inter-electrode dielectric material that has a thickness that is thicker than the dielectric material.

29. The method of claim 24 wherein forming an inter-electrode dielectric material further comprises using oxidation.

30. The method of claim 24 wherein forming an inter-electrode dielectric material further comprises using oxidation and deposition.