Stress in trigate devices using complimentary gate fill materials

• US 8,362,566 B2
• Filed: 06/23/2008
• Issued: 01/29/2013
• Est. Priority Date: 06/23/2008
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Rakshit, Titash, Giles, Martin, Pillarisetty, Ravi, Kavalieros, Jack T.
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Karimy, Timor
• Application Number:
  US12/144,469
• Publication Number:
  US 20090315114A1
• Time in Patent Office: 1,681 Days
• Field of Search: 257/368, 257/308, 257/E27.06, 257/E21.616
• US Class Current: 257/368
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

Claims

1. A semiconductor device, comprising:

a first fin comprising an N-type material raised above a substrate, the first fin having a first top surface, a first pair of sidewalls and a first current flow direction along a first major axis of the first fin;

a second fin comprising a P-type material raised above the substrate, the second fin having a second top surface, a second pair of sidewalls and a second current flow direction along a second major axis of the second fin generally parallel to the first major axis;

a first gate dielectric layer wrapped around the first top surface and the first pair of sidewalls;

a first gate comprising an intrinsically compressively stressed copper metal fill, the first gate in direct contact with the first gate dielectric layer on the first top surface and on the first pair of sidewalls, the first gate aligned substantially perpendicular to the first major axis, wherein the intrinsic compressive stress of the first copper metal fill exerts a tensile stress upon the first top surface and the first pair of sidewalls in the first current flow direction along the first major axis;

a second gate dielectric layer wrapped around the second top surface and the second pair of sidewalls; and

a second gate comprising an intrinsically tensilely stressed tungsten metal fill, the second gate in direct contact with the second gate dielectric layer on the second top surface and on the second pair of sidewalls, the second gate aligned substantially perpendicular to the second major axis, wherein the intrinsic tensile stress of the tungsten metal fill exerts a compressive stress upon the second top surface and the second pair of sidewalls in the second current flow direction along the second major axis.

2. The semiconductor device of claim 1, wherein the first gate has a depth of 10-100 nm.

3. The semiconductor device of claim 1, wherein the second gate has a depth of 10-100 nm.

4. The semiconductor device of claim 1, wherein the tensile stress exerted upon the first channel is substantially unequal to the compressive stress exerted upon the second channel.

5. The semiconductor device of claim 1, wherein the copper metal fill is intrinsically 1% stressed compared to a relaxed state.