Controlling the shape of source/drain regions in FinFETs
First Claim
1. An integrated circuit structure comprising:
- insulation regions comprising top surfaces; and
a fin field-effect transistor (FinFET) comprising;
a semiconductor fin over and adjacent to the insulation regions;
a gate dielectric on a top surface, and extending on sidewalls, of the semiconductor fin;
a gate electrode on the gate dielectric; and
a source/drain region over the insulation regions and adjoining the semiconductor fin, wherein the source/drain region comprises;
a first semiconductor region comprising silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region, and wherein the first semiconductor region comprises an up-slant facet and a down-slant facet; and
a second semiconductor region comprising silicon and the element, wherein the element has a second atomic percentage in the second semiconductor region with the second atomic percentage being lower than the first atomic percentage, wherein the second semiconductor region comprises a first portion on the up-slant facet and has a first thickness, and wherein a second portion of the second semiconductor region on the down-slant facet has a second thickness smaller than the first thickness.
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Accused Products
Abstract
An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.
254 Citations
18 Claims
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1. An integrated circuit structure comprising:
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insulation regions comprising top surfaces; and a fin field-effect transistor (FinFET) comprising; a semiconductor fin over and adjacent to the insulation regions; a gate dielectric on a top surface, and extending on sidewalls, of the semiconductor fin; a gate electrode on the gate dielectric; and a source/drain region over the insulation regions and adjoining the semiconductor fin, wherein the source/drain region comprises; a first semiconductor region comprising silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region, and wherein the first semiconductor region comprises an up-slant facet and a down-slant facet; and a second semiconductor region comprising silicon and the element, wherein the element has a second atomic percentage in the second semiconductor region with the second atomic percentage being lower than the first atomic percentage, wherein the second semiconductor region comprises a first portion on the up-slant facet and has a first thickness, and wherein a second portion of the second semiconductor region on the down-slant facet has a second thickness smaller than the first thickness. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit structure comprising:
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a silicon substrate; two shallow trench isolation (STI) regions in the silicon substrate and facing each other, with a portion of the silicon substrate therebetween; a silicon fin over, and horizontally between, the two STI regions; a gate dielectric on a top surface, and extending on sidewalls, of the silicon fin; a gate electrode on the gate dielectric; and a source/drain stressor comprising at least a portion over and horizontally between the two STI regions, wherein the source/drain stressor contacts the silicon fin and comprises; a first SiGe region having a first germanium atomic percentage, wherein the first SiGe region comprises an up-slant facet on a (111) plane, and a down-slant facet on an additional (111) plane; and a second SiGe region with a second germanium atomic percentage lower than the first germanium atomic percentage, wherein the second SiGe region comprises a portion on the up-slant facet, and wherein substantially no portion of the second SiGe region extends on the down-slant facet. - View Dependent Claims (10, 11, 12, 13)
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14. An integrated circuit structure comprising:
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a silicon substrate; two shallow trench isolation (STI) regions in the silicon substrate and facing each other, with a portion of the silicon substrate therebetween; a silicon fin over, and horizontally between, the two STI regions; a gate dielectric on a top surface, and extending on sidewalls, of the silicon fin; a gate electrode on the gate dielectric; and a source/drain stressor comprising at least a portion over and horizontally between the two STI regions, wherein the source/drain stressor contacts the silicon fin and comprises; a first SiGe region having a first germanium atomic percentage of germanium to silicon and germanium, wherein the first SiGe region has an up-slant facet on a (111) plane, and a down-slant facet on an additional (111) plane; and a first germano-silicide with a second germanium atomic percentage of germanium to silicon and germanium, wherein the second germanium atomic percentage is lower than the first germanium atomic percentage, and wherein the first germano-silicide is on the up-slant facet. - View Dependent Claims (15, 16, 17, 18)
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Specification