Semiconductor chip with coil element over passivation layer
First Claim
Patent Images
1. A chip comprising:
- a substrate;
a first patterned circuit layer over said substrate, wherein said first patterned circuit layer comprises a first copper layer and a first metal layer at a bottom surface and a sidewall of said first copper layer, wherein said first patterned circuit layer comprises a first coil; and
a second patterned circuit layer over said substrate, wherein said second patterned circuit layer comprises a metal trace, wherein said second patterned circuit layer comprises a second metal layer and a third metal layer on said second metal layer, wherein said third metal layer has a sidewall not covered by said second metal layer.
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Abstract
A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer.
121 Citations
30 Claims
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1. A chip comprising:
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a substrate; a first patterned circuit layer over said substrate, wherein said first patterned circuit layer comprises a first copper layer and a first metal layer at a bottom surface and a sidewall of said first copper layer, wherein said first patterned circuit layer comprises a first coil; and a second patterned circuit layer over said substrate, wherein said second patterned circuit layer comprises a metal trace, wherein said second patterned circuit layer comprises a second metal layer and a third metal layer on said second metal layer, wherein said third metal layer has a sidewall not covered by said second metal layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21)
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20. A chip comprising:
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a substrate; a first patterned circuit layer over said substrate, wherein said first patterned circuit layer comprises a first copper layer and a first metal layer at a bottom surface and a sidewall of said first copper layer, wherein said first patterned circuit layer comprises a first coil; a first insulating layer over said substrate; a metal pad on said first insulating layer and over said substrate, wherein said metal pad comprises a second metal layer and a third metal layer on said second metal layer, wherein said third metal layer has a sidewall not covered by said second metal layer; a second insulating layer on a peripheral region of said metal pad and on said first insulating layer, wherein an opening in said second insulating layer is over a contact point and left and right regions of said metal pad, and said contact point and left and right regions are at a bottom of said opening, wherein said contact point is between said left and right regions; and a metal bump on said contact point, wherein said metal bump comprises a second copper layer, wherein said metal bump has a left sidewall spaced apart from a left sidewall of said opening, and said left region is between said left sidewall of said metal bump and said left sidewall of said opening, wherein said metal bump has a right sidewall spaced apart from a right sidewall of said opening, and said right region is between said right sidewall of said metal bump and said right sidewall of said opening. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification