Electronic devices with extended metallization layer on a passivation layer

• US 8,362,620 B2
• Filed: 08/26/2010
• Issued: 01/29/2013
• Est. Priority Date: 08/28/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Pagani, Alberto
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): Montalvo, Eva Yan
• Application Number:
  US12/869,377
• Publication Number:
  US 20110049728A1
• Time in Patent Office: 887 Days
• Field of Search: 257/673, 257/773, 257/E21.531, 257/E23.169
• US Class Current: 257/773
• CPC Class Codes: G01R 31/2818 using test structures on, or modifications of, the card under test, made for the purpose of testing, e.g. additional components or connectors G01R31/2805 takes precedence; printed circuits having, e.g. symbols, test patterns or visualisation means H05K1/0266
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/04073 Bonding areas specifically adapted for connectors of different types
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48147 : with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 : the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49109 : outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73203 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A method performs electrical testing and assembly of an electronic device on a wafer and comprising a pad made in an oxide layer covered by a passivation layer. The method includes connecting the electronic device to a testing apparatus; providing said electronic device with a metallization layer extending on the passivation layer from the pad to a non-active area of said wafer. The method comprises-performing the electrical testing on wafer of the electronic device by placing a probe of on a portion of the extended metallization layer; performing the cut of said wafer, reducing the extension of the metallization layer to the edge of the electronic device; embedding the device inside a package, forming on the metallization layer an electrical connection configured to connect the metallization layer to a circuit in said package.

Claims

1. An electronic device, comprising:

a wafer having a non-active area;

an insulating layer formed on the wafer;

a passivation layer covering the insulating layer;

a first pad positioned in the insulating layer;

an extended metallization layer extending on said passivation layer from said first pad to a position directly above the non-active area of said wafer; and

a through-silicon via positioned in the wafer, in correspondence with said first pad, and in contact with said extended metallization layer.

2. The electronic device according to claim 1, wherein said extended metallization layer extends from said first pad to an edge of said device.

3. The electronic device according to claim 1, wherein said extended metallization layer includes a blind via extending into the passivation layer and positioned at one of the following:

at an edge of said device adjacent to said non-active area;

inside an active area of said device; and

directly above said non-active area.

4. The electronic device according to claim 1, further comprising:

a second pad; and

a scribe line positioned between the first and second pads and directly above the non-active area, wherein said extended metallization layer extends from said first pad up to at least the second pad and on the scribe line.

5. A multichip device, comprising:

a package that includes a support element;

a first electronic device that includes;

a substrate having an edge;

a metallization layer positioned on the substrate and extended to the edge of the substrate; and

an electrical connection positioned on said metallization layer and configured to establish an electrical connection between the metallization layer and the support element; and

a second electronic device in stacked configuration with said first electronic device, wherein said metallization layer includes a blind via extending into said passivation layer.

6. The multichip device according to claim 5, wherein the first electronic device includes:

an insulating layer formed on the substrate;

a passivation layer covering the insulating layer; and

a pad positioned in the insulating layer, wherein the metallization layer extends on said passivation layer from said pad to the edge of said substrate.

7. The multichip device according to claim 5, comprising:

a through-silicon via positioned in the substrate, in correspondence with said pad, and in contact with said metallization layer.

8. An electronic device, comprising:

a semiconductor wafer having first and second device areas and a non-active area between the device areas;

an insulating layer formed on the device areas and on the non-active area of the wafer;

a passivation layer covering the insulating layer and positioned over the device areas and on the non-active area of the wafer;

a first pad positioned in the insulating layer and above the first device area; and

a first extended metallization layer extending on said passivation layer from said first pad to a first portion of the passivation layer directly above the non-active area of said wafer, the first extended metallization layer not being connected to any conductive structure directly above or in the non-active area of said wafer.

9. The electronic device according to claim 8, further comprising a second pad positioned in the insulating layer and above the second device area, wherein said first extended metallization layer extends from said first pad to said second pad.

10. The electronic device according to claim 8, further comprising:

a second pad positioned in the insulating layer and above the second device area; and

a second extended metallization layer extending on said passivation layer from said second pad to a second portion of the passivation layer directly above the non-active area of said wafer, the second extended metallization layer not being connected to any conductive structure directly above or in the non-active area of said wafer and being spaced apart from the first extended metallization layer directly above the non-active area of said wafer.

11. The electronic device according to claim 8, wherein said first extended metallization layer includes a blind via positioned at one of the following:

at an edge of said first device area adjacent to said non-active area;

directly above the first device area; and

directly above said non-active area.

12. The electronic device according to claim 8, comprising:

a through-silicon via positioned in the wafer, in correspondence with said first pad, and in contact with said extended metallization layer.

13. The electronic device according to claim 8, wherein said metallization layer includes a blind via extending into said passivation layer.

14. An electronic device, comprising:

a wafer having a non-active area;

a insulating layer formed on the wafer;

a passivation layer covering the insulating layer;

a first pad positioned in the insulating layer; and

an extended metallization layer extending on said passivation layer from said first pad to a position directly above the non-active area of said wafer, wherein said metallization layer includes a blind via extending into said passivation layer.

15. The electronic device according to claim 14, wherein said extended metallization layer extends from said first pad to an edge of said device.

16. The electronic device according to claim 14, comprising:

a through-silicon via positioned in the wafer, in correspondence with said first pad, and in contact with said extended metallization layer.

17. The electronic device according to claim 14, further comprising:

a second pad; and

a scribe line positioned between the first and second pads and directly above the non-active area, wherein said extended metallization layer extends from said first pad up to at least the second pad and on the scribe line.