3D semiconductor device including field repairable logics

• US 8,362,800 B2
• Filed: 10/13/2010
• Issued: 01/29/2013
• Est. Priority Date: 10/13/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Ze'ev
• Primary Examiner(s): TRAN, THIENVU V
• Application Number:
  US12/904,108
• Publication Number:
  US 20120194216A1
• Time in Patent Office: 839 Days
• Field of Search: 326 9- 13, 326 37- 41, 326/47, 326/101
• US Class Current: 326/12
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A three dimensional semiconductor device is described with two transistor layers overlaid. The first transistor layer comprises a plurality of flip-flops each having an input and an output, wherein the inputs are selectively coupleable to the second transistor layer.

Claims

1. A system comprising:

a semiconductor device comprising a first transistor layer and a second transistor layer overlaying the first transistor layer, and

a plurality of circuits each performing a comparison between a signal generated by transistors of the first transistor layer and a signal generated by transistors of the second transistor layer;

wherein said first transistor layer comprises a plurality of flip-flops each having an input and an output,

wherein the inputs or the outputs are selectively coupleable to the second transistor layer, and are connectable to either output of a logic circuit constructed by said second transistors or to at least one flip-flop constructed by said second transistors,

wherein the plurality of flip-flop inputs or outputs are selectively coupled to the second transistor layer through a plurality of multiplexers, and

wherein the at least one flip-flop input or output is selectively coupled to the first transistor layer through the plurality of multiplexers.

2. A system according to claim 1, wherein the plurality of flip-flop inputs or outputs are selectively coupled to the second transistor layer by programming the semiconductor device.

3. A system according to claim 1, further comprising:

a controller to perform testing of a portion of said device.

4. A system according to claim 1, further comprising:

a signal from each of said plurality of flip-flop inputs or outputs coupled to the second transistor layer.

5. A system according to claim 1, further comprising:

logic circuits comprising transistors of the first transistor layer that are selectively replaceable by logic circuits comprising transistors on the second transistor layer.

6. A system comprising:

a semiconductor device comprising a first transistor layer comprising first transistors and a second transistor layer overlaying the first transistor layer and comprising second transistors,

wherein said first transistor layer comprises a plurality of sequential cells according to a net-list constructed by said first transistors,

wherein each sequential cell has an input and an output,

wherein each sequential cell input or output is selectively coupled to logic circuits constructed by said second transistors of said second transistor layer,

wherein each sequential cell input or output is selectively coupled to said logic circuits by programming the semiconductor device, and

wherein the sequential cell inputs or outputs are selectively coupled to the logic circuits through a plurality of multiplexers each configured to selectively replace a signal generated by the inputs or outputs of the sequential cells by a signal generated by the second transistors of the second transistor layer.

7. A system according to claim 6, further comprising:

a controller to perform testing of a portion of said device.

8. A system according to claim 6, further comprising:

a plurality of signals generated by said second transistor layer which are selectively coupled to the inputs or outputs of the plurality of sequential cells.

9. A system according to claim 8, further comprising:

wherein each of the plurality of signals is selectively coupled to the inputs or outputs of the plurality of sequential cells by programming the semiconductor device.

10. A system according to claim 9, wherein the plurality of signals generated by said second transistor layer are selectively coupled to the inputs or outputs of the plurality of sequential cells through a plurality of multiplexers.

11. A system according to claim 6, further comprising:

a logic circuit comprising transistors of the first transistor layer selectively replaceable by a logic circuit comprising transistors of the second transistor layer.

12. A system according to claim 6, further comprising:

a plurality of programmable elements to control said plurality of multiplexers.

13. A system according to claim 6, further comprising:

a plurality of circuits each comparing a signal generated by transistors of the first transistor layer and a signal generated by transistors of the second transistor layer.