Capacitance sensing circuit

• US 8,363,033 B2
• Filed: 06/14/2010
• Issued: 01/29/2013
• Est. Priority Date: 03/08/2010
• Status: Active Grant

• Current Assignee: Chunghwa Picture Tubes Limited
• Original Assignee: Chunghwa Picture Tubes Limited
• Inventors: Chen, Ke-Horng, Chen, Chi-Lin, Chen, Chih-Chung, Liu, Chia-Lin, Li, Huai-An, Mo, Chi-Neng, Wang, Shih-Wei
• Primary Examiner(s): Shankar, Vijay
• Application Number:
  US12/814,497
• Publication Number:
  US 20110216031A1
• Time in Patent Office: 960 Days
• Field of Search: 345173-178, 345/691, 178 1801- 1807, 178 2001- 2004
• US Class Current: 345/174
• CPC Class Codes: G06F 3/0418 for error correction or compensation, e.g. based on parallax, calibration or alignment
• CPC Class Codes: G06F 3/044 by capacitive means

Abstract

A capacitance sensing circuit for a touch panel includes an analog capacitance-detecting circuit, a PWM-to-digital circuit and a self-calibration circuit. The analog capacitance-detecting circuit detects the capacitance of the touch panel based on a charging current, and converts the detected capacitance into a PWM control signal. The PWM-to-digital circuit converts the PWM control signal into a sensing count value based on a clock signal. The self-calibration circuit adjusts the value of the charging current or the frequency of the clock signal according to the difference between the range of the sensing count value and a predetermined detecting range. The predetermined detecting range can thus be adjusted for matching the range of the sensing count value.

Claims

1. A capacitance sensing circuit, comprising:

an analog capacitance-detecting circuit configured to detect a touch capacitance of a touch panel when a touch action occurs according to a charging current and convert a detected value of the touch capacitance into a pulse width modulation (PWM) control signal;

a PWM-to-digital circuit configured to convert the PWM control signal into a sensing count value according to a clock signal; and

a self-calibration counter configured to adjust the charging current or the clock signal according to a difference between the sensing count value and a predetermined detecting range, thereby adjusting the predetermined detecting range for matching a range of the sensing count value;

wherein the analog capacitance-detecting circuit comprises;

a first switch controlled by the PWM control signal and including;

a first end for receiving the charging current;

a second end; and

a control end for receiving the PWM control signal;

a second switch controlled by a first control signal and including;

a first end coupled to the second end of the first switch;

a second end coupled to the panel for providing a ramp voltage corresponding to the touch capacitance; and

a control end for receiving the first control signal;

a third switch controlled by a second control signal and including;

a first end coupled to the second end of the second switch;

a second end coupled to a negative bias voltage; and

a control end for receiving the second control signal, wherein the first control signal and the second control signal have opposite phases; and

a comparator configured to generate the PWM control signal according to the ramp voltage and a reference voltage, the comparator including;

a first input end for receiving the reference signal;

a second input end coupled to the first end of the second switch; and

an output end coupled to the control end of the first switch for providing the PWM control signal.

2. The capacitance sensing circuit of claim 1, wherein the self-calibration counter comprises:

an input-range calibrator configured to generate a range conversion ratio according to a difference between the sensing count value and the predetermined detecting range; and

a digital current source configured to generate the charging current and adjust the charging current according to the range conversion ratio.

3. The capacitance sensing circuit of claim 2, wherein the input-range calibrator comprises:

a subtractor configured to provide an actual count value by subtracting the sensing count value by a baseline count value associated with a stray capacitance of the panel;

a maximum value register configured to store a maximum count value corresponding to an upper limit of the predetermined detecting range;

a minimum value register configured to store a minimum count value corresponding to a lower limit of the predetermined detecting range;

a comparator configured to determine a difference between a range of the sensing count value and the predetermined detecting range by comparing the actual count value with the maximum count value and the minimum count value; and

a range-adjusting circuit configured to;

control the digital control current source according to the range conversion ratio in order to increase the charging current when the range of the sensing count value exceeds the predetermined detecting range;

or

control the digital control current source according to the range conversion ratio in order to reduce the charging current when the range of the sensing count value does not exceed the predetermined detecting range.

4. The capacitance sensing circuit of claim 3, wherein the input-range calibrator further comprises:

a counter configured to adjust a duty cycle of the range-adjusting circuit.

5. The capacitance sensing circuit of claim 3, wherein the PWM-to-digital circuit comprises:

a phase-adjusting unit configured to generate the clock signal; and

an adder configured to receive the PWM control signal from the analog capacitance-detecting circuit and the clock signal from the phase-adjusting unit, detect a value of the PWM control signal when triggered by the clock signal, and increase the sensing count value when the PWN control signal is at a predetermined level.

6. The capacitance sensing circuit of claim 1, wherein the PWM-to-digital circuit comprises:

an adder configured to receive the PWM control signal from the analog capacitance-detecting circuit and the clock signal from the self-calibration circuit, detect a value of the PWM control signal when triggered by the clock signal, and increase the sensing count value when the PWN control signal is at a predetermined level.

7. The capacitance sensing circuit of claim 1, wherein the self-calibration counter comprises:

an input-range calibrator configured to generate a range conversion ratio according to a difference between the sensing count value and the predetermined detecting range; and

a digital control oscillator configured to generate the clock signal and adjust a frequency of the clock signal according to the range conversion ratio.

8. The capacitance sensing circuit of claim 7, wherein the input-range calibrator comprises:

a subtractor configured to provide an actual count value by subtracting the sensing count value by a baseline count value associated with a stray capacitance of the panel;

a maximum value register configured to store a maximum count value corresponding to an upper limit of the predetermined detecting range;

a minimum value register configured to store a minimum count value corresponding to a lower limit of the predetermined detecting range;

a comparator configured to determine a difference between a range of the sensing count value and the predetermined detecting range by comparing the actual count value with the maximum count value and the minimum count value; and

a range-adjusting circuit configured to;

control the digital control oscillator according to the range conversion ratio in order to reduce the frequency of the clock signal when the range of the sensing count value exceeds the predetermined detecting range;

or

control the digital control oscillator according to the range conversion ratio in order to increase the frequency of the clock signal when the range of the sensing count value does not exceed the predetermined detecting range.

9. The capacitance sensing circuit of claim 8, wherein the input-range calibrator further comprises:

a counter configured to adjust a duty cycle of the range-adjusting circuit.