Semiconductor device

• US 8,363,452 B2
• Filed: 11/02/2010
• Issued: 01/29/2013
• Est. Priority Date: 11/06/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Kato, Kiyoshi
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US12/917,564
• Publication Number:
  US 20110134683A1
• Time in Patent Office: 819 Days
• Field of Search: 365/149, 365/72, 365/63, 365/145, 365/189.09, 365/189.11, 365/230.06, 365/227
• US Class Current: 365/149
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/70 : the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

Disclosed is a semiconductor device functioning as a multivalued memory device including: memory cells connected in series; a driver circuit selecting a memory cell and driving a second signal line and a word line; a driver circuit selecting any of writing potentials and outputting it to a first signal line; a reading circuit comparing a potential of a bit line and a reference potential; and a potential generating circuit generating the writing potential and the reference potential. One of the memory cells includes: a first transistor connected to the bit line and a source line; a second transistor connected to the first and second signal line; and a third transistor connected to the word line, bit line, and source line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor is connected to one of source and drain electrodes of the second transistor.

Claims

1. A semiconductor device comprising:

a source line;

a bit line;

a first signal line;

a plurality of second signal lines;

a plurality of word lines;

a plurality of memory cells connected in series between the source line and the bit line;

a first driver circuit configured to drive the plurality of second signal lines and the plurality of word lines in such a manner that a memory cell is selected from the plurality of memory cells in accordance with an address signal input to the first driver circuit,

a second driver circuit configured to select and output any of a plurality of writing potentials to the first signal line;

a reading circuit supplied with a potential of the bit line and a plurality of reference potentials and comparing the potential of the bit line and the plurality of reference potentials to read data; and

a potential generating circuit generating the plurality of writing potentials and the plurality of reference potentials and supplying the plurality of writing potentials and the plurality of reference potentials to the second driver circuit and the reading circuit,

wherein one of the plurality of memory cells comprises;

a first transistor including a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor including a second gate electrode, a second source electrode, and a second drain electrode; and

a third transistor including a third gate electrode, a third source electrode, and a third drain electrode,

wherein the first transistor is provided over a substrate containing a semiconductor material,

wherein the second transistor includes an oxide semiconductor layer, and

wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,

wherein the source line, the first source electrode, and the third source electrode are electrically connected to one another,

wherein the bit line, the first drain electrode, and the third drain electrode are electrically connected to one another,

wherein the first signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein one of the plurality of second signal lines and the second gate electrode are electrically connected to each other, and

wherein one of the plurality of word lines and the third gate electrode are electrically connected to each other.

2. The semiconductor device according to claim 1 further comprising a capacitor electrically connected to the first gate electrode and the one of the second source electrode and the second drain electrode.

4. The semiconductor device according to claim 1 further comprising a boosting circuit supplying a potential to the potential generating circuit.

6. The semiconductor device according to claim 1 further comprising:

a first selection line;

a second selection line;

a fourth transistor including a fourth gate electrode and being electrically connected to the first selection line at the fourth gate electrode; and

a fifth transistor including a fifth gate electrode and being electrically connected to the second selection line at the fifth gate electrode,

wherein the bit line is electrically connected to the first drain electrode and the third drain electrode through the fourth transistor, and

wherein the source line is electrically connected to the first source electrode and the third source electrode through the fifth transistor.

8. The semiconductor device according to claim 1,

wherein the first transistor comprises:

a channel formation region provided in the substrate containing the semiconductor material;

impurity regions provided with the channel formation region sandwiched therebetween;

a first gate insulating layer over the channel formation region;

the first gate electrode over the first gate insulating layer; and

the first source electrode and the first drain electrode electrically connected to the impurity regions.

10. The semiconductor device according to claim 1,

wherein the second transistor comprises:

the second gate electrode over the substrate containing the semiconductor material;

a second gate insulating layer over the second gate electrode;

the oxide semiconductor layer over the second gate insulating layer; and

the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.

12. The semiconductor device according to claim 1,

wherein the substrate containing the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

14. The semiconductor device according to claim 1,

wherein the semiconductor material is silicon.

16. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer contains an In—

Ga—

Zn—

O-based oxide semiconductor material.

18. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

20. The semiconductor device according to claim 1,

wherein hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

22. The semiconductor device according to claim 1,

wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.

3. A semiconductor device comprising:

a source line;

a bit line;

a first signal line;

a plurality of second signal lines;

a plurality of word lines;

a plurality of memory cells connected in series between the source line and the bit line;

a first driver circuit configured to drive the plurality of second signal lines and the plurality of word lines in such a manner that a memory cell is selected from the plurality of memory cells in accordance with an address signal input to the first driver circuit and any of a plurality of reference potentials input to the first driver circuit is selected and output to one selected word line;

a second driver circuit configured to select and output any of a plurality of writing potentials to the first signal line;

a reading circuit connected to the bit line configured to read data by reading conductance of the selected memory cell; and

a potential generating circuit generating the plurality of writing potentials and the plurality of reference potentials and supplying the plurality of writing potentials and the plurality of reference potentials to the second driver circuit,

wherein one of the plurality of memory cells comprises;

a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and

a capacitor,

wherein the first transistor is provided over a substrate containing a semiconductor material,

wherein the second transistor includes an oxide semiconductor layer, and

wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to one another,

wherein the source line and the first source electrode are electrically connected to each other,

wherein the bit line and the first drain electrode are electrically connected to each other,

wherein the first signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other,

wherein one of the plurality of second signal lines and the second gate electrode are electrically connected to each other, and

wherein one of the plurality of word lines and the other of the electrodes of the capacitor are electrically connected to each other.

5. The semiconductor device according to claim 3 further comprising a boosting circuit supplying a potential to the potential generating circuit.

7. The semiconductor device according to claim 3 further comprising:

a first selection line;

a second selection line;

a third transistor including a third gate electrode and being electrically connected to the first selection line at the third gate electrode; and

a fourth transistor including a fourth gate electrode and being electrically connected to the second selection line at the fourth gate electrode,

wherein the bit line is electrically connected to the first drain electrode through the third transistor, and

wherein the source line is electrically connected to the first source electrode through the fourth transistor.

9. The semiconductor device according to claim 3,

wherein the first transistor comprises:

a channel formation region provided in the substrate containing the semiconductor material;

impurity regions provided with the channel formation region sandwiched therebetween;

a first gate insulating layer over the channel formation region;

the first gate electrode over the first gate insulating layer; and

the first source electrode and the first drain electrode electrically connected to the impurity regions.

11. The semiconductor device according to claim 3,

wherein the second transistor comprises:

the second gate electrode over the substrate containing the semiconductor material;

a second gate insulating layer over the second gate electrode;

the oxide semiconductor layer over the second gate insulating layer; and

the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.

13. The semiconductor device according to claim 3,

wherein the substrate containing the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.

15. The semiconductor device according to claim 3,

wherein the semiconductor material is silicon.

17. The semiconductor device according to claim 3,

wherein the oxide semiconductor layer contains an In—

Ga—

Zn—

O-based oxide semiconductor material.

19. The semiconductor device according to claim 3,

wherein the oxide semiconductor layer contains a crystal of In₂Ga₂ZnO₇.

21. The semiconductor device according to claim 3,

wherein hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×

10¹⁹ atoms/cm³.

23. The semiconductor device according to claim 3,

wherein off-state current of the second transistor is less than or equal to 1×

10<sup>−

13</sup> A.