Nonvolatile semiconductor memory device and method of reading data from nonvolatile semiconductor memory device

• US 8,363,466 B2
• Filed: 12/22/2010
• Issued: 01/29/2013
• Est. Priority Date: 12/26/2009
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Shinozaki, Naoharu, Taguchi, Masao, Sugimoto, Satoru
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Nguyen, Nam
• Application Number:
  US12/976,355
• Publication Number:
  US 20110157978A1
• Time in Patent Office: 769 Days
• Field of Search: 365/185.02, 365/185.26, 365/189.011
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (−3.5 V or 0 V). This configuration eliminates an application of a pulsed voltage to the word line at the time of reading, making it possible to reduce an influence of read disturbance. In addition, even when a voltage in a range from a power source voltage to a ground voltage or a voltage over the power source voltage is required at the time of reading, it becomes a voltage about 1.5 times an absolute value of the power source voltage. Therefore, a voltage step-up circuit having a large number of stages is not required, and as a result, it is possible to achieve a reduced operation time with a low power consumption.

Claims

1. A nonvolatile semiconductor memory device comprising:

a string including a plurality of memory cells connected in series, each of the memory cells having a field effect transistor that stores information in a nonvolatile manner;

a bit line connected to one end of the string;

a source line connected to other end of the string;

a plurality of word lines each connected to an associated one of gate electrodes of the field effect transistors;

a word driver that drives the word lines; and

a first power source line and a second power source line that supply a first voltage and a second voltage to the word driver, respectively, wherein

the first voltage is a voltage between a third voltage of a first one of the field effect transistors that stores first information and a fourth voltage of a second one of the field effect transistors that stores second information,

the second voltage is higher than each of the first, third, and forth voltages,

the word driver supplies the second voltage to the word lines in a ready time when the string is not accessed, and

the word driver supplies the first voltage to a gate electrode of a target field effect transistor to be accessed among the field effect transistors and supplies the second voltage to gate electrodes of other field effect transistors not to be accessed, in a read time when the string is to be accessed.

2. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the second voltage is a voltage in which the field effect transistors are brought into electrically conductive state regardless that the first information or the second information are stored.

3. The nonvolatile semiconductor memory device as claimed in claim 2, wherein the third and fourth voltages are lower than a ground voltage.

4. The nonvolatile semiconductor memory device as claimed in claim 3, wherein

the first voltage is lower than the ground voltage, and

the second voltage is the ground voltage.

5. The nonvolatile semiconductor memory device as claimed in claim 2, wherein the field effect transistors are depletion type.

6. The nonvolatile semiconductor memory device as claimed in claim 2, wherein

the first voltage is a low voltage lower than a voltage at a high voltage side supplied from outside to the nonvolatile semiconductor memory device, and

the second voltage is the voltage at the high voltage side.

7. The nonvolatile semiconductor memory device as claimed in claim 6, wherein

the third voltage is lower than a ground voltage,

the fourth voltage is higher than the ground voltage,

the first voltage is the low voltage, and

the second voltage is the voltage at the high voltage side.

8. The nonvolatile semiconductor memory device as claimed in claim 7, wherein the first voltage is the ground voltage.

9. The nonvolatile semiconductor memory device as claimed in claim 1, further comprising a first control circuit that generates a first control signal in response to a command to access the string supplied from outside of the nonvolatile semiconductor memory device, wherein

the word driver transitions a voltage of a word line corresponding to the target field effect transistor from the second voltage to the first voltage, and maintains voltages of word lines corresponding to the other field effect transistors not to be accessed so as to be the second voltage, in response to the first control signal.

10. The nonvolatile semiconductor memory device as claimed in claim 9, further comprising:

a charging circuit that charges the bit line to a predetermined voltage in response to the first control signal; and

a second control circuit that controls a first select transistor, a second select transistor, and the charging circuit in response to the first control signal, wherein

the string includes;

the first select transistor that electrically connects one end of the field effect transistors connected in series and one end of the string; and

the second select transistor that electrically connects other end of the field effect transistors connected in series and other end of the string.

11. The nonvolatile semiconductor memory device as claimed in claim 10, wherein, in response to the command, the first and second control circuits activate the charging circuit,

activate, after activating the charging circuit, the first select transistor,

activate, after activating the first select transistor, the target field effect transistor,

and activate, after activating the target field effect transistor, the second select transistor.

12. The nonvolatile semiconductor memory device as claimed in claim 10, wherein, in response to the command, the first and second control circuits activate the charging circuit and the first select transistor simultaneously,

activate, after activating the charging circuit, the target field effect transistor,

and activate, after activating the target field effect transistor, the second select transistor.

13. The nonvolatile semiconductor memory device as claimed in claim 10, wherein, in response to the command, the first and second control circuits activate the charging circuit,

activate, after activating the charging circuit, the target field effect transistor,

activate, after activating the target field effect transistor, the first select transistor,

and activate, after activating the first select transistor, the second select transistor.

14. The nonvolatile semiconductor memory device as claimed in claim 10, further comprising a third control circuit controls the threshold value of the first and/or second selection transistors by Erase and/or Program.

15. The nonvolatile semiconductor memory device as claimed in claim 14, wherein

the third control circuit controls the threshold value of the first and/or second selection transistors corresponding to a initialization command or power supplied from the outside of the nonvolatile semiconductor memory device.

16. A system comprising the nonvolatile semiconductor memory device as claimed in claim 1, and a controller which controls the nonvolatile semiconductor memory device.

17. A method of controlling a nonvolatile semiconductor memory device comprising:

receiving from outside a command that reads data from a memory cell;

transitioning a voltage of a first word line corresponding to a first memory cell to be accessed as a target for reading data from a second voltage to a first voltage that is lower than the second voltage, in response to the command; and

maintaining voltages of a plurality of second word lines corresponding to a plurality of second memory cells connected to the first memory cell in series so as to be the second voltage, in response to the command.

18. The method of controlling a nonvolatile semiconductor memory device as claimed in claim 17, wherein

the first voltage is lower than a ground voltage, and

the second voltage is the ground voltage.

19. The method of controlling a nonvolatile semiconductor memory device as claimed in claim 17, wherein

the first voltage is a ground voltage, and

the second voltage is a voltage at a high voltage side supplied from outside to the nonvolatile semiconductor memory device.

20. The method of controlling a nonvolatile semiconductor memory device as claimed in claim 17, further comprising:

charging a bit line connected to one end of a string that includes the first memory cell and the second memory cells in response to the command;

after charging, first activating including activating a first select transistor that connects one end of the first memory cell and the second memory cells connected in series and one end of the string;

after first activating, second activating including activating the first word line; and

after second activating, third activating including activating a second select transistor that connects other end of the first memory cell and the second memory cells connected in series and other end of the string.

21. The method of controlling a nonvolatile semiconductor memory device as claimed in claim 17, further comprising:

charging a bit line connected to one end of a string that includes the first memory cell and the second memory cells and first activating including activating the first select transistor that connects one end of the first memory cell and the second memory cells connected in series and one end of the string in response to the command;

after charging and first activating, second activating including activating the first word line; and

after second activating, third activating including activating a second select transistor that connects other end of the first memory cell and the second memory cells connected in series and other end of the string.

22. The method of controlling a nonvolatile semiconductor memory device as claimed in claim 17, further comprising:

charging a bit line connected to one end of a string that includes the first memory cell and the second memory cells in response to the command;

after charging, first activating including activating the first word line;

after first activating, second activating including activating the first select transistor that connects one end of the first memory cell and the second memory cells connected in series and one end of the string; and

after second activating step, third activating including activating a second select transistor that connects other end of the first memory cell and the second memory cells connected in series and other end of the string.

23. A device comprising:

a non-volatile memory array including a plurality of cells and a plurality of word lines associated with the cells; and

a controller controlling, in a ready state, the non-volatile memory array so that the word lines establish a second voltage, and

the controller further controlling, in a read operation state, the non-volatile memory array so that a first one of the word lines establish a first voltage different from the second voltage and second ones of the word lines establish the second voltage, the first one of the word lines being associated with a cell to be read, and the second ones of the word lines being associated with cells not to be read.

24. The device of claim 23, wherein the first voltage is lower than the second voltage.

25. The device of claim 24, where one of the first and the second voltage is a ground voltage.

26. The device of claim 24, where the first voltage is a ground voltage and the second voltage is a power supply voltage which is supplied to the device.

27. The device of claim 23, wherein when the cell to be read is rendered conductive in response to the establishing of the first voltage in the read operation state, a bit line associated with the cell to be read establishes a first read voltage,

and wherein when the cell to be read is rendered non-conductive in response to the establishing of the first voltage in the read operation state, the bit line associated with the cell to be read establishes a second read voltage, the second read voltage being higher than the first read voltage.

28. The device of claim 23, wherein the controller changes a state of the non-volatile memory array from the ready state to the read operation state in response to a read command.

29. The device of claim 23, wherein the non-volatile memory array further comprises:

a plurality of bit lines associated with the cells;

a source line;

a plurality pairs of first and second select transistors configured to select, when activated, ones of the cells, the ones of the cells being coupled between the first and second select transistors in a corresponding one of the pairs, the first select transistor being coupled to a corresponding one of the bit lines, and the second select transistor being coupled to the source line;

and wherein the device further comprise;

a charging circuit configured to charge, when activated, one of the bit lines.

30. The device of claim 29, wherein the first voltage on the first one of the word lines is established, after the first select transistor is activated and after the charging circuit is activated.

31. The device of claim 30, wherein the first select transistor and the charging circuit are activated simultaneously.

32. The device of claim 29, wherein the first voltage on the first one of the word lines is established, before the first select transistor is activated and after the charging circuit is activated.

33. The device of claim 29, wherein the controller is configured to select one of first, second, and third modes to read data from the nonvolatile memory array in the read operation state,

the first mode being a mode where the first voltage on the first one of the word lines is established, after the first select transistor is activated and after the charging circuit is activated,

the second mode being a mode where the first voltage on the first one of the word lines is established, after the first select transistor and the charging circuit are activated simultaneously, and

the third mode being a mode where the first voltage on the first one of the word lines is established, before the first select transistor is activated and after the charging circuit is activated.

34. The device of claim 23, wherein the non-volatile memory array are configured in a NAND type.