Non-volatile memory unit cell with improved sensing margin and reliability

• US 8,363,475 B2
• Filed: 03/30/2010
• Issued: 01/29/2013
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Chen, Hsin-Ming, Wang, Shih-Chen, Ching, Wen-Hao, Lai, Yen-Hsin, Lu, Hau-Yan, Yang, Ching-Sung
• Primary Examiner(s): Hoang, Huan
• Assistant Examiner(s): HOANG, TRI M
• Application Number:
  US12/750,650
• Publication Number:
  US 20110242893A1
• Time in Patent Office: 1,036 Days
• Field of Search: 365/185.18, 365/185.09
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

A non-volatile memory unit cell includes a first transistor pair and first and second control gates. The first transistor pair includes first and second transistors that are connected in series and of the same type. The first and second transistors have a first floating polysilicon gate and a second floating polysilicon gate, respectively. The first control gate is coupled to the first floating polysilicon gate through a tunneling junction and the second control gate is coupled to the second floating polysilicon gate through another tunneling junction.

Claims

1. An only-one-polysilicon layer non-volatile memory unit cell comprising:

a first N-type transistor pair having a first transistor and a second transistor that are connected in series along a read path and of the same type, the first transistor and the second transistor having a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated and the charges movement are identically the same in the first floating polysilicon gate of the first transistor and the second floating polysilicon gate of the second transistor when the non-volatile memory unit cell is at write or data deleting mode;

a first control gate coupled to the first floating polysilicon gate through a first capacitive coupling junction;

a second control gate coupled to the second floating polysilicon gate through a second capacitive coupling junction;

a first source/drain junction of the first transistor is coupled to a second source/drain junction of the second transistor, wherein the first source/drain junction and the second source/drain junction are physically isolated from external power supplies; and

a P-type transistor pair having a third transistor and a fourth transistor that are connected in parallel and of the same type, the third transistor and the fourth transistor having a third floating polysilicon gate and a fourth floating polysilicon gate, respectively, wherein the third floating polysilicon gate and the fourth floating polysilicon gate are electrically or physically isolated, the third floating polysilicon gate physically coupled to the first floating polysilicon gate, the fourth floating polysilicon gate physically coupled to the second floating polysilicon gate.

2. The only-one-polysilicon layer non-volatile memory unit cell according to claim 1, further comprising:

a third control gate coupled to the first and third floating polysilicon gates through a first tunneling junction; and

a fourth control gate coupled to the second and fourth floating polysilicon gates through a second tunneling junction.

3. The only-one-polysilicon layer non-volatile memory unit cell according to claim 1, wherein the read current conducts from the first transistor to the second transistor directly when the non-volatile memory unit cell is operating at read mode.

4. The only-one-polysilicon layer non-volatile memory unit cell according to claim 1, wherein the charges movement are identically the same in all floating polysilicon gates of the first transistor pair and the second transistor pair when the non-volatile memory unit cell is at write or data deleting mode.

5. The only-one-polysilicon layer non-volatile memory unit cell according to claim 1, wherein the first transistor and second transistor serve as a fault tolerance cell and do self-repair automatically if stored charges in one of the transistors move away from the corresponding storage medium.

6. The only-one-polysilicon layer non-volatile memory unit cell according to claim 1, wherein the salicide protection layers are added on top of all the floating polysilicon gates for charge retention improvement.

7. The only-one-polysilicon layer non-volatile memory unit cell according to claim 1, wherein the self-referencing scheme can be implemented by performing the current comparison between current generated by the N-transistor pair and the current generated by the P-transistor pair under appropriate bias settings.

8. The only-one-polysilicon layer non-volatile memory unit cell according to claim 2, wherein the first coupling junction, the second coupling junction, the first tunneling junction and the second tunneling junction are constructed by transistors.

9. The only-one-polysilicon layer non-volatile memory unit cell according to claim 8, wherein the first and second transistors are native transistors or receiving additional lightly doped drain (LDD) implantation to reduce the threshold voltages.