Memory device, manufacturing method and operating method of the same

• US 8,363,476 B2
• Filed: 01/19/2011
• Issued: 01/29/2013
• Est. Priority Date: 01/19/2011
• Status: Expired

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting, Chen, Shih-Hung
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/009,464
• Publication Number:
  US 20120182808A1
• Time in Patent Office: 741 Days
• Field of Search: 365/130
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

Claims

1. A memory device, comprising:

a substrate;

a plurality of stacked structures disposed on the substrate, wherein each of the stacked structures comprises a string selection line, a word line, a ground selection line and an insulating line, the string selection line, the word line and the ground selection line are separated from each other by the insulating line;

a channel element disposed between the stacked structures;

a dielectric element disposed between the channel element and the stacked structure;

a source element disposed between an upper surface of a substrate and the lower surface of the channel element; and

a bit line disposed on the upper surface of the channel element.

2. The memory device according to claim 1, wherein the source element and the substrate are separated from each other by the dielectric element, the substrate is used as a bottom gate.

3. The memory device according to claim 1, wherein the string selection line, the word line and the ground selection line have a first type conductivity, the source element, the channel element and the bit line have a second type conductivity opposite to the first type conductivity, the channel element has a dopant concentration smaller than dopant concentrations that the source element and the bit line have.

4. The memory device according to claim 1, wherein the bit line, the string selection line, the word line and the ground selection line have a first type conductivity, the source element and the channel element have a second type conductivity opposite to the first type conductivity, the channel element has a dopant concentration smaller than a dopant concentration that the source element has.

5. The memory device according to claim 1, wherein the bit line has a first type conductivity, the channel element has a second type conductivity opposite to the first type conductivity.

6. The memory device according to claim 1, wherein the channel element and the bit line form a PN diode.

7. The memory device according to claim 1, wherein the source element comprises a source layer covering the substrate.

8. The memory device according to claim 1, wherein the channel element comprises a plurality of channel lines, the source element comprises a plurality of source lines,

one of the source lines below the channel lines on the same sidewall of the stacked structure is continuously extended;

the source lines below the channel lines on the opposite sidewalls of the stacked structure are separated from each other.

9. The memory device according to claim 1, wherein the channel element comprises a plurality of channel lines, the source element comprises a plurality of source lines, the channel line has a long side perpendicular to a long side that the source line has.

10. A method for manufacturing a memory device, comprising:

disposing a plurality of stacked structures on a substrate, wherein each of the stacked structures comprises a string selection line, a word line, a ground selection line and an insulating line, the string selection line, the word line and the ground selection line are separated from each other by the insulating line;

disposing a channel element between the stacked structures;

disposing a dielectric element between the channel element and the stacked structure;

disposing a source element between an upper surface of the substrate and a lower surface of the channel element; and

disposing a bit line on the upper surface of the channel element.

11. The method for manufacturing the memory device according to claim 10, wherein the stacked structures has a space therebetween, the source element comprises a source line, the method for manufacturing the memory device comprises:

forming a dielectric element on the substrate and the stacked structures exposed by the space;

forming a conductive material for filling the space; and

removing a portion of the conductive material for forming the source line and the channel element, wherein the source line and the channel element are disposed in the space, the source line and the substrate are separated from each other by the dielectric element.

12. The method for manufacturing the memory device according to claim 11, wherein the conductive material is extended on the stacked structure, the bit line is formed by a method comprising:

doping a portion of the conductive material extended on the stacked structure; and

removing a portion of the doped conductive material for forming the bit line.

13. The method for manufacturing the memory device according to claim 10, wherein the source element comprises a source layer covering the substrate, the method for manufacturing the memory device comprises:

alternately stacking a plurality of sacrificial layers and a plurality of insulating layers;

forming a first opening in the alternately-stacked sacrificial layers and insulating layers;

forming the channel element by an epitaxial growth on the source layer exposed by the first opening;

forming a second opening in the alternately-stacked sacrificial layers and insulating layers;

removing the sacrificial layer exposed by the second opening for forming a slit exposing the channel element;

forming the dielectric element exposed by the slit; and

forming a conductive material filling in the slit for forming the string selection line, the word line and the ground selection line.

14. The method for manufacturing the memory device according to claim 13, wherein the source layer and the channel element are composed of a single crystal material, and the channel element is formed by an epitaxial growth.

15. The method for manufacturing the memory device according to claim 13, wherein the source layer is a single crystal silicon, the insulating line is an oxide, the sacrificial layer is a silicon nitride, the second opening exposes the source layer and the insulating line, the sacrificial layer exposed by the second opening is removed by a method using a hot H3PO4.

16. A method for operating a memory device, comprising:

providing a memory device comprising;

a substrate;

a plurality of stacked structures disposed on the substrate, wherein each of the stacked structures comprises a string selection line, a word line, a ground selection line and an insulating line, the string selection line, the word line and the ground selection line are separated from each other by the insulating line;

a channel element comprising a plurality of channel lines, the channel lines are disposed between the stacked structures and separated from each other;

a dielectric element disposed between the channel lines and the stacked structures;

a source element disposed between an upper surface of the substrate and a lower surface of the channel lines; and

a bit line disposed on a upper surface of the channel element; and

selecting at least one of the channel lines to be turned on.

17. The method for operating the memory device according to claim 16, wherein the string selection line, the word line and the ground selection line have a first type conductivity, the source element, the channel element and the bit line have a second type conductivity opposite to the first type conductivity,

the channel line is turned on by a method comprising:

applying a first bias voltage to the string selection lines of the stacked structures on the two opposite sidewalls of the selected channel line.

18. The method for operating the memory device according to claim 17, further comprising applying a second bias voltage to the string selection line of the stacked structure on one sidewall of the channel line not selected and to be turned off, wherein the turned off channel line and the turned-on channel line have the common string selection line that the first bias voltage applied to, the first bias voltage is opposite to the second bias voltage.

19. The method for operating the memory device according to claim 18, wherein the first type conductivity is P type conductivity, the second type conductivity is N type conductivity, the first bias voltage is a positive bias voltage, and the second bias voltage is a negative bias voltage.

20. The method for operating the memory device according to claim 17, further comprising applying a second bias voltage to the string selection lines of the stacked structures on the opposite sidewalls of the channel line not selected and to be turned off.

21. The method for operating the memory device according to claim 20, wherein the first bias voltage and the second bias voltage are respectively applied to a portion adjacent to the channel line to be turned on and a portion adjacent to the channel line to be turned off of the single string selection line.

22. The method for operating the memory device according to claim 16, further comprising applying a third bias voltage and a fourth bias voltage different from each other to the word lines of the stacked structures on the two opposite sidewalls of the channel line.

23. The method for operating the memory device according to claim 22, wherein the third bias voltage is V_PGM or V_READ, the fourth bias voltage is zero.

24. The method for operating the memory device according to claim 16, wherein the bit line, the string selection line, the word line and the ground selection line have a first type conductivity, the source element and the channel lines have a second type conductivity,

the selected channel line is turned on by a method comprising:

applying a zero voltage or grounding the source element below the selected channel line.

25. The method for operating the memory device according to claim 16, further comprising floating and applying a fifth bias voltage to the source element below the channel line unselected and to be turned off.

26. The method for operating the memory device according to claim 25, wherein the first type conductivity is P type conductivity, the second type conductivity is N type conductivity, the fifth bias voltage is a positive bias voltage.