Programming a non-volatile memory

• US 8,363,491 B2
• Filed: 01/28/2011
• Issued: 01/29/2013
• Est. Priority Date: 01/28/2011
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Mu, Fuchen, Wang, Yanzhuo
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US13/016,522
• Publication Number:
  US 20120195124A1
• Time in Patent Office: 732 Days
• Field of Search: 365/185.03, 365/185.16, 365/185.28, 365/189.16
• US Class Current: 365/189.16
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

In a system having a plurality of non-volatile memory cells, a method includes performing hot carrier injection on a first non-volatile memory cell in a first mode of programming. In the first mode, current flows from a first current electrode to a second electrode of the first non-volatile memory cell and charge is transferred from the current to a floating gate of the first non-volatile memory cell at a location nearer the first current electrode than the second current electrode. The method further includes performing hot carrier injection on the first non-volatile memory cell in a second mode of programming. In the second mode, current flows from the second current electrode to the first electrode of the first non-volatile memory cell and charge is transferred from the current to the floating gate of the first non-volatile memory cell at a location nearer the second current electrode than the first current electrode.

Claims

1. A memory comprising:

a plurality of non-volatile memory cells, wherein each non-volatile memory cell has a floating gate, comprising a first column of the plurality of non-volatile memory cells, wherein the column is coupled to a first read source line and a first read bit line;

a switch for coupling the first read source line to a first source line and the first read bit line to a first bit line in a first program mode and coupling the first read source line to the first bit line and the first read bit line to the first source line in a second program mode; and

a decoder for coupling a program voltage to the first bit line in the first program mode and the second program mode for use in injecting charge into a floating gate of a non-volatile memory cell of the plurality of non-volatile memory cells in the first mode and in the second mode.

2. The memory of claim 1, wherein the decoder couples the program voltage to the first of a few bit lines when a non-volatile memory cell in the first of a few columns are selected to be programmed with high word line voltage.

3. The memory of claim 1, further comprising

a plurality of word lines coupled to the first column, wherein a non-volatile memory cell to be programmed is in a selected column and coupled to a word line selected from the plurality of word lines.

4. The memory of claim 1, wherein the switch provides coupling such that all programming for a programming cycle is in a selected one of a group consisting of the first mode and the second mode.

5. The memory of claim 1, wherein the switch provides coupling such that programming for a programming cycle alternates between the first mode and the second mode.

6. The memory of claim 1, wherein the first mode of programming is characterized by charge being distributed across the floating gate of a selected non-volatile memory cell after entering the floating gate on a first side of the floating gate and away from a second side of the floating gate and the second mode of programming is characterized by charge being distributed across the floating gate after entering on the second side of the floating gate and away from the first side of the floating gate.

7. A memory comprising:

a plurality of non-volatile memory cells, wherein each of the plurality of non-volatile memory cells includes a floating gate, a first current electrode, and a second current electrode; and

a program circuit having a first mode and a second mode, wherein in the first mode the program circuit applies a higher voltage to the first current electrode than the second current electrode of a selected non-volatile memory cell so that in the first mode charge is spread across the floating gate after entering on a first side of the floating gate nearest the first current electrode and in the second mode the program circuit applies a higher voltage to the second current electrode than the first current electrode so that in the second mode charge is spread across the floating gate after entering on a first side of the floating gate nearest the second current electrode.

8. The memory of claim 7, wherein:

the plurality of non-volatile memory cells comprise a column of non-volatile memory cells coupled to a read source line and a read drain line;

the program circuit comprises;

a switch coupled to the read source line and a read drain line;

a controller coupled to the switch;

a decoder coupled to the switch; and

a charge pump coupled to the decoder.

9. The memory of claim 8, wherein the controller directs the switch to provide a program voltage from the charge pump to a selected one of a group consisting of the read source line and the read drain line when a non-volatile memory cell from the column of non-volatile memory cells is selected for programming by the decoder.

10. The method of claim 7 wherein the program circuit programs the selected non-volatile memory cell by either exclusively a selected one of the first mode and the second mode or both the first mode and the second mode alternatively.