Methods and systems for DSP-based receivers
First Claim
1. A method, comprising:
- (a) receiving a data signal;
(b) generating N sampling signals, each of said N sampling signals having a respective phase;
(c) sampling said data signal with said N sampling signals to generate N samples;
(d) individually adjusting each of said N sampling signals to reduce one or more of sampling phase errors, gain errors, and offsets in said N samples; and
(e) generating a digital signal representative of said received data signal from said N samples.
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Accused Products
Abstract
Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.
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Citations
20 Claims
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1. A method, comprising:
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(a) receiving a data signal; (b) generating N sampling signals, each of said N sampling signals having a respective phase; (c) sampling said data signal with said N sampling signals to generate N samples; (d) individually adjusting each of said N sampling signals to reduce one or more of sampling phase errors, gain errors, and offsets in said N samples; and (e) generating a digital signal representative of said received data signal from said N samples. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A receiver, comprising:
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a timing recovery module that generates N sampling signals having time-staggered phases; an analog-to-digital converter (ADC) array of N ADC paths that receives a data signal and that samples said data signal according to said N sampling signals to generate N samples; and a compensation module configured to individually adjust each of said N ADC paths to reduce one or more of sampling phase errors, gain errors, and offsets in said N samples. - View Dependent Claims (17, 18, 19, 20)
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Specification