Software application striping

• US 8,364,744 B2
• Filed: 09/09/2009
• Issued: 01/29/2013
• Est. Priority Date: 02/05/2008
• Status: Active Grant

• Current Assignee: Nant Holdings IP, LLC (NantWorks, LLC)
• Original Assignee: Nant Holdings IP, LLC (NantWorks, LLC)
• Inventors: Wittenschlaeger, Thomas
• Primary Examiner(s): Lazaro, David
• Assistant Examiner(s): KIM, EDWARD J
• Application Number:
  US12/556,263
• Publication Number:
  US 20090327446A1
• Time in Patent Office: 1,238 Days
• Field of Search: 709213-216, 709201-203, 709204-207, 709/217, 709/219, 709220-221, 709227-229, 709/246, 709/200
• US Class Current: 709/201
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: G06F 9/54 Interprogram communication

Abstract

A distributed computing system comprising networking infrastructure and methods of executing an application on the distributed computing system is presented. Interconnected networking nodes offering available computing resources form a network fabric. The computing resources can be allocated from the networking nodes, including available processing cores or memory elements located on the networking nodes. A software application can be stored in a system memory comprising memory elements allocated from the nodes. The software application can be disaggregated into a plurality of executable portions that are striped across the allocated processing cores by assigning each core a portion to execute. When the cores are authenticated with respect to their portions, the cores are allowed to execute the portions by accessing the system memory over the fabric. While executing the software application, the networking nodes having the allocated cores concurrently forward packets through the fabric.

Claims

1. A distributed computing platform, comprising:

a plurality of interconnected networking switches forming a general data transport network between a first and second different device, each switch having a memory element and a multi-core processor;

a first processing core from a first switch of the networking switches and a second processing core from a second different switch of the networking switches;

a system memory comprising allocated memory elements from at least two of the switches where the system memory is addressable by the first and the second processing cores, and storing a software application; and

wherein executable portions of the software application are securely striped across the first and the second processing cores by distributing the executable portions to the cores in the different switches according to a secret distribution function secured via a secret key, where the secret distribution function governs placement of the executable portions on the cores in a manner that appear random.

2. The platform of claim 1, further comprising a cache local to the first processing core and storing instructions of a first executable portion of the executable portions.

3. The platform of claim 1, wherein the first switch and second switch comprise a heterogeneous mix of networking switches.

4. The platform of claim 1, further comprising a memory map of the system memory stored in the memory elements of the first switch and the second switch.

5. The platform of claim 1, wherein at least one of the executable portions comprises machine code executable by the first processing core.

6. The platform of claim 1, wherein the first switch is configured to execute on its multi-core processor at least two different executable portions of the software application.

7. The platform of claim 6, wherein the first switch is configured to execute on its multi-core processor at least three different executable portions of the software application.

8. The platform of claim 1, wherein at least two of the executable portions are mirrored portions, which configures the first and second processing cores to concurrently execute the mirrored portions.

9. The platform of claim 8, wherein the first processing core is configured to continue executing one of the mirrored portions upon loss of connectivity between the system memory and the second processing core.

10. The platform of claim 1, wherein at least two of the executable portions are different and comprise overlapping code segments.

11. The platform of claim 1, wherein the first and the second processing cores are configured to store results of execution of their respective executable portions in the system memory over the network.

12. The platform of claim 1, wherein the first processing cores is capable of executing its assigned executable portion while the first switch forwards packets from the first device to the second device.

13. The platform of claim 1, further comprising a first segment and a second segment partitioned from the system memory, where the first and the second segments are for exclusive use by the first and the second processing cores, respectively.

14. The platform of claim 1, wherein the networking switches form a distributed core fabric.

15. The platform of claim 1, wherein at least one of the first and the second devices is configured to store the software application in the system memory.