Fibre channel input/output data routing system and method

• US 8,364,854 B2
• Filed: 06/01/2011
• Issued: 01/29/2013
• Est. Priority Date: 06/01/2011
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bubb, Clinton E., Casper, Daniel F., Flanagan, John R.
• Primary Examiner(s): NGUYEN, TANH Q
• Application Number:
  US13/150,555
• Publication Number:
  US 20120311200A1
• Time in Patent Office: 608 Days
• Field of Search: None
• US Class Current: 710/5
• CPC Class Codes: G06F 13/12 using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus

Abstract

A computer program product is provided for performing input/output (I/O) processing at a host computer system. The computer program product is configured to perform: generating an address control structure for each of a plurality of consecutive data transfer requests specified by an I/O operation, each address control structure specifying a location in the local channel memory of a corresponding address control word (ACW) that includes an Offset field indicating a relative order of a data transfer request; generating and storing in local channel memory at least one ACW specifying one or more host memory locations for the plurality of consecutive data transfer requests and including an Expected Offset field indicating a relative order of an expected data transfer request; receiving a transfer request from the network interface and comparing the Offset field and the Expected Offset field to determine whether the data transfer request has been received in the correct order.

Claims

1. A computer program product for performing an input/output (I/O) processing operation at a host computer system configured for communication with a control unit, the computer program product comprising:

a non-transitory tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

obtaining information relating to an I/O operation at a channel subsystem in the host computer system, the channel subsystem including at least one channel having a channel processor and a local channel memory;

generating an address control structure for each of a plurality of consecutive data transfer requests specified by the I/O operation and forwarding each address control structure from the at least one channel to a network interface between the channel subsystem and at least one I/O device, each address control structure specifying a location in the local channel memory of a corresponding address control word (ACW), each address control structure including an Offset field indicating a relative order of a corresponding data transfer request relative to other data transfers in the plurality of consecutive data transfer requests;

generating at least one ACW specifying one or more host memory locations for the plurality of consecutive data transfer requests, and storing the at least one ACW in the local channel memory, the at least one ACW including an Expected Offset field indicating a relative order of an expected data transfer request;

forwarding an I/O command message to the at least one I/O device via the network interface;

responsive to the I/O command message, receiving a data transfer request from the network interface that includes the addressing information specified by a corresponding address control structure;

comparing, by a data router in the channel, the Offset field and the Expected Offset field to determine whether the data transfer request has been received in the correct order; and

responsive to determining that the data transfer request has been received in the correct order, accessing the at least one ACW by the data router and routing the data transfer request to the host memory location specified in the at least one ACW.

2. The computer program product of claim 1, wherein routing the data transfer request includes incrementing the Expected Offset field value by an amount corresponding a size of the data transfer request.

3. The computer program product of claim 1, wherein receiving the data transfer request includes routing the data transfer request to request queue that includes at least one of a Fetch Array Queue configured to hold two or more consecutive output data requests for output data in the host memory, and a Store Array Queue configured to hold two or more consecutive input data requests to store input data at the host memory.

4. The computer program product of claim 3, wherein receiving the data transfer request includes receiving each of the plurality of consecutive data transfer requests and storing each of the plurality of data transfer requests in the request queue in the order received and processing each of the plurality of data transfer requests from the request queue in the order received.

5. The computer program product of claim 4, wherein the method further comprises, in response to the Expected Offset field not matching the Offset field of the data transfer request, re-queuing the data transfer request at an end of the request queue.

6. The computer program product of claim 5, wherein the method further comprises:

processing one or more of the plurality of data transfer requests in order from the request queue until the data transfer request reaches the top of the request queue;

comparing the Expected Offset field to the Offset field of the data transfer request; and

responsive to the Expected Offset field matching the Offset field, accessing the at least one ACW by the data router and routing the data transfer request to the host memory location specified in the at least one ACW;

responsive to the Expected Offset field not matching the Offset field, discarding the corresponding data transfer requests and any other subsequent data transfer requests in the plurality of requests.

7. The computer program product of claim 5, wherein the method further comprises:

setting a time stamp and writing the time stamp into the data transfer request prior to re-queuing the data transfer request, wherein upon the data transfer request reaching the top of the request queue and the Expected Offset field not matching the Offset field, performing one of;

responsive to the time stamp exceeding a selected timeout value, discarding the data transfer request and any other subsequent data transfer requests in the plurality of requests; and

responsive to the time stamp not exceeding a selected timeout value, re-queuing the data transfer request at the end of the request queue.

8. The computer program product of claim 1, wherein the I/O operation is a transport mode operation, and obtaining information includes obtaining a transport command word (TCW) at the channel subsystem, the TCW including a transport command control block (TCCB) address field including an address of a TCCB, the TCCB including a plurality of device command words (DCW) that each includes an I/O command.

9. The computer program product of claim 1, wherein the network interface is a host bus adaptor (HBA).

10. An apparatus for performing an input/output (I/O) processing operation at a host computer system configured for communication with a control unit, the host computer system including a channel subsystem, the channel subsystem configured to communicate with the control unit via a network interface, the channel subsystem configured to perform:

obtaining information relating to an I/O operation at a channel subsystem in the host computer system, the channel subsystem including at least one channel having a channel processor and a local channel memory;

generating an address control structure for each of a plurality of consecutive data transfer requests specified by the I/O operation and forwarding each address control structure from the at least one channel to a network interface between the channel subsystem and at least one I/O device, each address control structure specifying a location in the local channel memory of a corresponding address control word (ACW), each address control structure including an Offset field indicating a relative order of a corresponding data transfer request relative to other data transfers in the plurality of consecutive data transfer requests;

generating at least one ACW specifying one or more host memory locations for the plurality of consecutive data transfer requests, and storing the at least one ACW in the local channel memory, the at least one ACW including an Expected Offset field indicating a relative order of an expected data transfer request;

forwarding an I/O command message to the at least one I/O device via the network interface;

responsive to the I/O command message, receiving a data transfer request from the network interface that includes the addressing information specified by a corresponding address control structure;

comparing, by a data router in the channel, the Offset field and the Expected Offset field to determine whether the data transfer request has been received in the correct order; and

responsive to determining that the data transfer request has been received in the correct order, accessing the at least one ACW by the data router and routing the data transfer request to the host memory location specified in the at least one ACW.

11. The apparatus of claim 10, wherein routing the data transfer request includes incrementing the Expected Offset field value by an amount corresponding a size of the data transfer request.

12. The apparatus of claim 10, wherein receiving the data transfer request includes routing the data transfer request to request queue that includes at least one of a Fetch Array Queue configured to hold two or more consecutive output data requests for output data in the host memory, and a Store Array Queue configured to hold two or more consecutive input data requests to store input data at the host memory.

13. The apparatus of claim 12, wherein receiving the data transfer request includes receiving each of the plurality of consecutive data transfer requests and storing each of the plurality of data transfer requests in the request queue in the order received and processing each of the plurality of data transfer requests from the request queue in the order received.

14. The apparatus of claim 13, wherein the apparatus is configured to further perform, in response to the Expected Offset field not matching the Offset field of the data transfer request, re-queuing the data transfer request at an end of the request queue.

15. The apparatus of claim 14, wherein the apparatus is configured to further perform:

processing one or more of the plurality of data transfer requests in order from the request queue until the data transfer request reaches the top of the request queue;

comparing the Expected Offset field to the Offset field of the data transfer request; and

responsive to the Expected Offset field matching the Offset field, accessing the at least one ACW by the data router and routing the data transfer request to the host memory location specified in the at least one ACW;

responsive to the Expected Offset field not matching the Offset field, discarding the corresponding data transfer requests and any other subsequent data transfer requests in the plurality of requests.

16. The apparatus of claim 14, wherein the apparatus is configured to further perform:

setting a time stamp and writing the time stamp into the data transfer request prior to re-queuing the data transfer request, wherein upon the data transfer request reaching the top of the request queue and the Expected Offset field not matching the Offset field, performing one of;

responsive to the time stamp exceeding a selected timeout value, discarding the data transfer request and any other subsequent data transfer requests in the plurality of requests; and

responsive to the time stamp not exceeding a selected timeout value, re-queuing the data transfer request at the end of the request queue.

17. The apparatus of claim 10, wherein the I/O operation is a transport mode operation, and obtaining information includes obtaining a transport command word (TCW) at the channel subsystem, the TCW including a transport command control block (TCCB) address field including an address of a TCCB, the TCCB including a plurality of device command words (DCW) that each includes an I/O command.