Asynchronous ID generation
First Claim
1. A method of assigning an identifier (ID) for a memory device configured in a daisy chain cascade arrangement having a plurality of devices, the method comprising:
- processing, at a first memory device in the daisy chain cascade arrangement, a command causing the first device to enter a mode for assigning an identifier;
asynchronously asserting an input to input a first value to the first memory device independent of a clock signal;
asynchronously producing a second value from the first value independent of a clock signal;
asynchronously asserting an output to output the second value from the first memory device to a second memory device in the daisy chain cascade arrangement independent of a clock signal, the output being configured to output control signals outside of the mode for assigning an identifier, the control signals being distinct from the first and second values; and
holding an ID established for the first memory device based on the first value.
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Accused Products
Abstract
A technique for automatically establishing device IDs for devices in a daisy chain cascade arrangement. For each device, a write ID operation is initiated at the device to cause the device to enter a generate/write ID mode. While in this mode, a first value is input to the device. The device generates a second value from the first value. The device outputs the generated second value from the device to a next device in the daisy chain cascade which uses the second value as a first value for the next device. The device then establishes its ID from the first value. The process is repeated for all devices in the daisy chain cascade arrangement.
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Citations
16 Claims
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1. A method of assigning an identifier (ID) for a memory device configured in a daisy chain cascade arrangement having a plurality of devices, the method comprising:
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processing, at a first memory device in the daisy chain cascade arrangement, a command causing the first device to enter a mode for assigning an identifier; asynchronously asserting an input to input a first value to the first memory device independent of a clock signal; asynchronously producing a second value from the first value independent of a clock signal; asynchronously asserting an output to output the second value from the first memory device to a second memory device in the daisy chain cascade arrangement independent of a clock signal, the output being configured to output control signals outside of the mode for assigning an identifier, the control signals being distinct from the first and second values; and holding an ID established for the first memory device based on the first value. - View Dependent Claims (2, 3, 4, 5)
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6. A memory device configured in a daisy chain cascade arrangement having a plurality of memory devices, the memory device comprising:
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control circuitry configured to process a command causing the device to enter a mode for assigning an identifier; input circuitry configured to input, asynchronously and independent of a clock signal, a first value into the memory device; output circuitry configured to output, asynchronously and independent of a clock signal, a second value generated asynchronously and independent of a clock signal from the first value to a second memory device in the daisy chain cascade via one or more outputs of the device, the output circuitry asserting an output configured to output control signals outside of the mode for assigning an identifier, the control signals being distinct from the first and second values; and holding circuitry configured to hold an identifier established (ID) for the memory device based on the first value. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A daisy chain cascade arrangement having a plurality of devices, the arrangement comprising:
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a first memory device comprising; control circuitry configured to process a command causing the first memory device to enter a mode for assigning an identifier; input circuitry configured to input, asynchronously and independent of a clock signal, a first value into the first memory device; producing circuitry configured to produce, asynchronously and independent of a clock signal, a second value from the first value; output circuitry configured to output, asynchronously and independent of a clock signal, the second value to a second memory device, the output circuitry asserting an output configured to output control signals outside of the mode for assigning an identifier, the control signals being distinct from the first and second values; and holding circuitry configured to hold a first identifier (ID) established for the first memory device, the first ID based on the first value; and a second memory device comprising; control circuitry configured to process a command causing the second memory device to enter a mode for assigning an identifier; input circuitry configured to input the second value into the second memory device; producing circuitry configured to produce a third value from the second value; output circuitry configured to output the third value to a third memory device, the output circuitry asserting an output configured to output control signals outside of the mode for assigning an identifier, the control signals being distinct from the first and second values; and holding circuitry configured to hold a second identifier (ID) established for the second memory device, the second ID based on the second value. - View Dependent Claims (13, 14, 15, 16)
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Specification