Delegating a poll operation to another device
First Claim
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1. An apparatus comprising:
- a core to generate a registration message to delegate a poll operation to an input/output (IO) interconnect;
a coherent interconnect coupled to the core;
the IO interconnect coupled to the coherent interconnect, the IO interconnect including a poll table having a plurality of entries each having a register address field to store a register address received in a registration message, a destination address field to store a destination address in a system memory received in the registration message, and an initial value field to store an initial value associated with the register address received in the registration message; and
at least one device coupled to the IO interconnect to perform an operation for an application executing on the core and including at least one status register, the IO interconnect to poll the at least one status register responsive to information in a poll table entry, and to issue a write transaction to the destination address if a polled value of the at least one status register differs from the initial value, the IO interconnect further including a poll delegation logic to issue a read request to the at least one device at a predetermined interval to perform the poll.
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Abstract
In one embodiment, the present invention includes a method for handling a registration message received from a host processor, where the registration message delegates a poll operation with respect to a device from the host processor to another component. Information from the message may be stored in a poll table, and the component may send a read request to poll the device and report a result of the poll to the host processor based on a state of the device. Other embodiments are described and claimed.
35 Citations
17 Claims
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1. An apparatus comprising:
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a core to generate a registration message to delegate a poll operation to an input/output (IO) interconnect; a coherent interconnect coupled to the core; the IO interconnect coupled to the coherent interconnect, the IO interconnect including a poll table having a plurality of entries each having a register address field to store a register address received in a registration message, a destination address field to store a destination address in a system memory received in the registration message, and an initial value field to store an initial value associated with the register address received in the registration message; and at least one device coupled to the IO interconnect to perform an operation for an application executing on the core and including at least one status register, the IO interconnect to poll the at least one status register responsive to information in a poll table entry, and to issue a write transaction to the destination address if a polled value of the at least one status register differs from the initial value, the IO interconnect further including a poll delegation logic to issue a read request to the at least one device at a predetermined interval to perform the poll. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system comprising:
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a first integrated circuit including; at least one core including a first logic to execute a first instruction to set up a monitored address in a memory and a second logic to cause the at least one core to enter a low power state when a predetermined instruction follows the first instruction; a first coherent interconnect coupled to the at least one core; a first input/output (IO) interconnect including a poll table to store a tuple including a register identifier of a register in an intellectual property (IP) block coupled to the first IO interconnect, the monitored address in the memory, and an initial value associated with the register, and a delegation logic to receive a delegation message from the at least one core, and based on the tuple, obtain a current value of the register until the current value differs from the initial value and responsive to the difference write data to the monitored address; and the IP block coupled to the first IO interconnect including the register and to perform a function for an application executing on the at least one core; and the memory coupled to the first integrated circuit via a memory interconnect, wherein the at least one core is to exit the low power state responsive to the data being written to the destination address of the memory and to continue execution of the application at a next instruction following the predetermined instruction. - View Dependent Claims (9, 10)
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11. A method comprising:
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receiving a registration message from a host processor in an interconnect coupled between the host processor and a device, the registration message to delegate a poll operation with respect to the device to the interconnect; storing information regarding a device monitored location, a memory monitored address, and an initial value of the device monitored location in a poll table associated with the interconnect; and using a poll delegation logic of the interconnect to send a read request from the interconnect to the device to poll the device and to compare the initial value with a device value obtained from the device monitored location, and reporting a result of the poll to the host processor if the device value is different than the initial value. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification