USB port connected to multiple USB compliant devices

• US 8,364,870 B2
• Filed: 03/31/2011
• Issued: 01/29/2013
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Van Antwerpen, Hans, Letourneur, Herve
• Primary Examiner(s): Alrobaye, Idriss N
• Assistant Examiner(s): Franklin, Richard B
• Application Number:
  US13/076,733
• Publication Number:
  US 20120084470A1
• Time in Patent Office: 670 Days
• Field of Search: 710/1, 710/62, 710/63, 710/72, 710/100
• US Class Current: 710/63
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 2213/0042 Universal serial bus [USB]

Abstract

At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port.

Claims

1. A device, comprising:

a downstream port including a first conductor directly connected to a USB 3.0 capable device and including a second conductor simultaneously directly connected to a USB 2.0 compliant device, wherein the downstream port is configured to communicate USB 3.0 signals with the USB 3.0 capable device via the first conductor and to communicate USB 2.0 signals with the USB 2.0 capable device via the second conductor.

2. The device of claim 1, wherein the one downstream port includes a first set of conductors and a second set of conductors, wherein the first set of conductors are configured to directly connect to the USB 3.0 capable device and to convey USB 3.0 signals to the USB 3.0 capable device and the second set of conductors are configured to directly connect to the USB 2.0 compliant device and to convey USB 2.0 signals to the USB 2.0 compliant device.

3. The device of claim 1, further comprising a controller coupled to a bus, and wherein the downstream port includes a first data path between the bus and the USB 3.0 capable device and a second data path between the bus and the USB 2.0 compliant device.

4. The device of claim 3, wherein the first and second data paths are separate and distinct from one another.

5. The device of claim 1, further comprising first and second controllers, wherein the downstream port includes first and second data paths, and wherein the first data path couples the USB 3.0 capable device to the first controller and the second data path couples the USB 2.0 compliant device to the second controller.

6. The device of claim 1, wherein the downstream port is configured to convey the USB 3.0 signals and the USB 2.0 signals simultaneously.

7. The device of claim 1, further comprising a host controller, a hub controller, a system on chip that includes the host controller or the hub controller.

8. The device of claim 1, further comprising a USB controller configured to alternate between communicating with the USB 3.0 capable device using USB 3.0 signals and communicating with the USB 2.0 compliant device using USB 2.0 signals.

9. A device, comprising:

a downstream port configured to simultaneously provide a first connection to a USB 3.0 capable device using USB 3.0 signals and a second connection to a USB 2.0 compliant device using USB 2.0 signals; and

a USB controller configured to alternate between communicating with the USB 3.0 capable device using the USB 3.0 signals and communicating with the USB 2.0 compliant device using the USB 2.0 signals.

10. The device of claim 9, wherein the first connection to the USB 3.0 capable device is independent of the second connection to the USB 2.0 compliant device.

11. The device of claim 9, wherein the downstream port is configured to receive simultaneous communications from the USB 3.0 capable device and the USB 2.0 compliant device.

12. The device of claim 9, wherein the USB 3.0 capable device is a video chipset and the USB 2.0 compliant device is an Ethernet chipset.

13. The device of claim 9, further comprising first and second USB controllers coupled to the downstream port, the first controller configured to handle the USB 3.0 signals and the second controller configured to handle the USB 2.0 signals.

14. The device of claim 9, comprising a USB hub or a USB splitter.

15. A system, comprising:

a USB hub device positioned in a housing and that includes an upstream interface and at least one downstream interface; and

an individual downstream interface that has a first set of USB 3.0 conductors directly connected to a USB 3.0 compliant chip set and a second set of USB 2.0 conductors simultaneously directly connected to a USB 2.0 compliant chip set.

16. The system of claim 15, wherein the individual downstream interface is configured to provide a first data path and a first buffer for the USB 3.0 compliant chip set and a second data path and a second buffer for the USB 2.0 compliant chip set.

17. The system of claim 16, wherein the USB 3.0 conductors are soldered to the USB 3.0 compliant chip set and the second set of USB 2.0 conductors are soldered to the USB 2.0 compliant chip set.

18. The system of claim 15, wherein the USB hub device includes a controller and wherein the first set of USB 3.0 conductors provide a first data path between the USB 3.0 compliant chip set and the controller and wherein the second set of USB 2.0 conductors provide a second data path between the USB 2.0 compliant chip set and the controller.

19. The system of claim 18, wherein the first data path and the second data path allow simultaneous communications from the USB 3.0 compliant chip set to the controller and from the USB 2.0 compliant chip set to the controller.

20. The system of claim 16, wherein the USB 3.0 compliant chip set is a video chipset that includes a video port positioned on the housing and wherein the USB 2.0 compliant chip set is an Ethernet chipset that includes an Ethernet port on the housing.

21. The system of claim 15, wherein the USB hub device is configured to alternate between communicating with the USB 3.0 compliant chip set using USB 3.0 signals and communicating with the USB compliant chip set using USB 2.0 signals.

22. A method, comprising:

communicating with a USB 3.0 compliant device via a downstream port; and

simultaneously communicating with a USB 2.0 compliant device via the downstream port, wherein the downstream port is simultaneously directly connected to both the USB 3.0 compliant device and the USB 2.0 compliant device.