Memory module with reduced access granularity

• US 8,364,926 B2
• Filed: 02/29/2012
• Issued: 01/29/2013
• Est. Priority Date: 05/02/2006
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Hampel, Craig E., Ware, Frederick A.
• Primary Examiner(s): Thai, Tuan
• Assistant Examiner(s): LI, ZHUO H
• Application Number:
  US13/408,950
• Publication Number:
  US 20120159061A1
• Time in Patent Office: 335 Days
• Field of Search: 711/4, 711/100, 711/103, 711111-112, 711114-115, 711147-150, 711/152, 711167-168, 710 20- 21, 710 36- 38, 710/200, 710/305, 710/309
• US Class Current: 711/168
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 2212/656 Address space sharing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09227 Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Claims

1. An apparatus that exchanges data with a memory controller over a data path having a width, the apparatus comprising:

a first rank of memory;

a second rank of memory;

the first and second ranks of memory each operable to communicate data with the memory controller over the data path;

where each of the first rank of memory and the second rank of memory are operable in a selective one of

a rank-wide access mode, in which the first rank of memory and the second rank of memory exchange first and second data respectively at mutually exclusive times with the memory controller, where the first and second data each occupy more than half the width of the data path, and

a sub-rank access mode, in which a first subrank of the first rank of memory and a first subrank of the second rank of memory exchange third and fourth data, respectively, at mutually exclusive times with the memory controller over a first subset of the width of the data path, and in which a second subrank of the first rank of memory and second subrank of the second rank of memory exchange fifth and sixth data, respectively, at mutually exclusive times with the memory controller over a second subset of the width of the data path, the third, fourth, fifth and sixth data each occupying no more than half of the data path width, the third data associated with an independent memory command from the fifth data and the fourth data associated with an independent memory command from the sixth data.

2. The apparatus of claim 1, where:

the first rank of memory is mounted to a first side of a substrate;

the second rank of memory is mounted to a second side of the substrate, opposite the first side;

the first and second ranks are operable to receive commands from the memory controller via a shared command/address path; and

commands associated with the third data and the fourth data are received from the memory controller via the shared command/address path.

3. The apparatus of claim 1, where the apparatus is operable to permit first and second independent, concurrent memory accesses that exchange data respectively over the first and second subsets of the width of the data path, and respectively with one of the first subranks and one of the second subranks during the sub-rank access mode.

4. The apparatus of claims 1, where the apparatus is embodied as at least one memory module and further comprises a common signaling terminal of each memory module in electrical communication with each of the first rank and the second rank, and where the apparatus further comprises a respective signaling path operable to communicate a respective externally-provided chip select signal to each of the first subrank and the second subrank, respectively.

5. The apparatus of claim 4, where the apparatus is further characterized by respective signal paths for each of first, second, third and fourth externally-provided chips select signals, each of the first, second, third and fourth externally provided chip select signals respectively dedicated to the first subrank of the first rank of memory, the second subrank of the first rank of memory, the first subrank of the second rank of memory and the second subrank of the second rank of memory, the first and second chip select signals operable in lock-step for rank-wide access mode and in time-staggered fashion for the sub-rank access mode, and the third and fourth chip select signals operable in lock-step for rank-wide access mode and in time-staggered fashion for the sub-rank access mode.

6. The apparatus of claim 1, further comprising at least one circuit operable to store a programmable sampling latency for a subset of the subranks between assertion of a shared chip select signal and sampling of a shared command/address path.

7. The apparatus of claim 1, where the first subrank and the second subrank of the first rank of memory each receive a chip select signal, and where the apparatus further comprises by a circuit operable to define a polarity for an exclusive one of the first subrank or the second subrank, so as to control whether the exclusive one responds to a high or low value of the chip select signal.

8. The apparatus of claim 1, further comprising a circuit operable to store a sub-rank specific identifier associated with at least one of the first subrank of the first rank of memory, the second subrank of the first rank of memory, the first subrank of the second rank of memory or the second subrank of the second rank of memory, the circuit operable to determine whether an ID value associated with an incoming command matches the sub-rank specific identifier and, if so, operable to enable command execution by the at least one subrank associated with the sub-rank specific identifier.

9. The apparatus of claim 1, further comprising at least one circuit operable to store a programmable output latency for a subset of the subranks between receipt of a command and responsive output of data, the apparatus operable in dependence on the programmable output latency as to permit simultaneous output of the third data and the fifth data responsive to respective commands received at different times over a shared command/address path.

10. The apparatus of claim 1, further comprising at least one buffer operable to, in the sub-rank access mode, receive commands over a shared command/address path and direct commands to exactly one first subrank or one second subrank.

11. The apparatus of claim 1, further comprising at least one buffer operable to, in the sub-rank access mode, receive commands over a shared command/address path and direct commands to exactly one of the first subrank of the first rank of memory, the second subrank of the first rank of memory, the first subrank of the second rank of memory or the second subrank of the second rank of memory.

12. The apparatus of claim 11, where the apparatus includes at least one memory module, each memory module having at least one signaling terminal adapted for connection to a module connector, the at least one signaling terminal in electrical communication with both of the first rank of memory and the second rank of memory, each memory module mounting at least one buffer operable to, in the sub-rank access mode, receive commands over a shared command/address path and direct commands to exactly one of the first subrank of the corresponding rank of memory or the second subrank of the corresponding rank of memory.

13. The apparatus of claim 1, where the apparatus further comprises a memory module, the memory module comprising at least one signaling terminal adapted for connection to a module connector, the at least one signaling terminal in electrical communication with both of the first rank of memory and the second rank of memory, the memory module also comprising a common substrate that mounts at least the first subrank of the first rank of memory and the first subrank of the second rank of memory, and at least one via defined in the common substrate that provides for a shared signaling connection for each of the first subrank of the first rank of memory and the first subrank of the second rank of memory to receive command information from the memory controller.

14. The apparatus of claim 13, where each one of the first subrank of the first rank of memory, the second subrank of the first rank of memory, the first subrank of the second rank of memory, and the second subrank of the second rank of memory each includes at least one dynamic random access memory device.

15. The apparatus of claim 1, where each one of the first subrank of the first rank of memory, the second subrank of the first rank of memory, the first subrank of the second rank of memory, and the second subrank of the second rank of memory each includes at least one dynamic random access memory device.

16. A method of operating memory, the memory comprising a first rank and a second rank that share a common data path with a memory controller, the common data path having a width, each of the first rank and the second rank operable to exchange respective first and second data with the memory controller in a rank-wide access mode where the first and second data each occupy more than half the data path width in association with commands received over a shared command path, the method comprising:

configuring the memory for sub-rank memory access in which a first subrank of the first rank of memory and a first subrank of the second rank of memory exchange third and fourth data, respectively, at mutually exclusive times with the memory controller over a first subset of the width of the data path, and in which a second subrank of the first rank of memory and a second subrank of the second rank of memory exchange fifth and sixth data, respectively, at mutually exclusive times with the memory controller over a second subset of the width of the data path, the third, fourth, fifth and sixth data each occupying no more than half of the width, the third data associated with an independent memory command from the fifth data and the fourth data associated with an independent memory command from the sixth data.

17. The method of claim 16, further comprising configuring the memory to provide sub-rank access to concurrently output over the respective subsets of the common data path the third data from the first subrank of the first rank of memory and the sixth data from the second subrank of the second rank of memory, responsive to respective memory commands transmitted at different times over the shared command path.

18. The method of claim 16, where at least one of the first rank or the second rank further comprises at least one buffer, the method further comprising configuring the at least one buffer to provide sub-rank access by directing commands received from over a shared command/address path to exactly one first subrank or one second subrank.

19. The method of claim 18, where each of the first rank and the second rank comprises at least one buffer, the method further comprising configuring the respective buffers to provide sub-rank access by directing commands received from over the shared command/address path to exactly one of the first subrank of the first rank of memory, the second subrank of the first rank of memory, the first subrank of the second rank of memory or the second subrank of the second rank of memory.

20. The method of claim 19, where the first rank of memory and the second rank of memory each include discrete random access memory (DRAM) devices, at least one of the DRAM devices for the first rank and at least one of the DRAM devices for the second rank mounted respectively to opposite sides of a common substrate.

21. An apparatus, comprising:

memory comprising a first rank and a second rank, each of the first rank and the second rank sharing a common data path for connection to a memory controller, the common data path having a width, each of the first rank and the second rank operable to exchange respective first and second data with a memory controller in a rank-wide access mode where the first and second data each occupy more than half the data path width in association with commands received over a shared command path; and

,

circuitry for each rank of memory operable to direct sub-rank memory access commands within the respective rank, such that a first subrank of the first rank of memory and a first subrank of the second rank of memory exchange third and fourth data, respectively, at mutually exclusive times with the memory controller over a first subset of the width of the data path, and such that a second subrank of the first rank of memory and a second subrank of the second rank of memory exchange fifth and sixth data, respectively, at mutually exclusive times with the memory controller over a second subset of the width of the data path, the third, fourth, fifth and sixth data each occupying no more than half of the width, the third data associated with an independent memory command from the fifth data and the fourth data associated with an independent memory command from the sixth data.