Fin-like field effect transistor (FinFET) device and method of manufacturing same

• US 8,367,498 B2
• Filed: 10/18/2010
• Issued: 02/05/2013
• Est. Priority Date: 10/18/2010
• Status: Active Grant

• Current Assignee: Parabellum Strategic Opportunities Fund LLC (Parabellum Capital LLC)
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Chih-Hao, Xu, Jeff J.
• Primary Examiner(s): GHYKA, ALEXANDER G
• Application Number:
  US12/906,820
• Publication Number:
  US 20120091528A1
• Time in Patent Office: 841 Days
• Field of Search: 438/279, 438/268
• US Class Current: 438/268
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a fin structure over the semiconductor substrate, the fin structure including a first material portion over the semiconductor substrate and a second material portion over the first material portion; forming a gate structure over a portion of the fin structure, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween; removing the second material portion from the source and drain regions of the fin structure; and after removing the second material portion, forming a third material portion in the source and drain regions of the fin structure.

Claims

1. A method comprising:

providing a semiconductor substrate;

forming a fin structure over the semiconductor substrate, the fin structure at least partially embedded within a dielectric layer and including a first semiconductor material portion over the semiconductor substrate and a second semiconductor material portion over the first semiconductor material portion;

forming a gate structure over a portion of the fin structure and the dielectric layer, such that the gate structure traverses the fin structure, thereby separating a source region and a drain region of the fin structure, wherein the source and drain regions of the fin structure define a channel therebetween;

after forming the gate structure, removing the second semiconductor material portion from the source and drain regions of the fin structure, wherein removing the second semiconductor material portion from the source and drain regions of the fin structure includes forming a trench in the source and drain regions of the fin structure, the trench extending below a top surface of the dielectric layer; and

after removing the second semiconductor material portion, forming a third material portion in the source and drain regions of the fin structure.

2. The method of claim 1 wherein the removing the second semiconductor material portion from the source and drain regions of the fin structure includes completely etching the second semiconductor material portion from the source and drain regions of the fin structure, thereby exposing the first semiconductor material portion in the source and drain regions of the fin structure.

3. The method of claim 2 wherein the forming the third material portion in the source and drain regions of the fin structure includes epitaxially growing a semiconductor material over the exposed first material portion.

4. The method of claim 1 wherein the removing the second semiconductor material portion from the source and drain regions of the fin structure includes partially etching the second semiconductor material portion from the source and drain regions of the fin structure.

5. The method of claim 4 wherein the forming the third material portion in the source and drain regions of the fin structure includes epitaxially growing a semiconductor material over a remaining second material portion.

6. The method of claim 1 wherein:

the removing the second semiconductor material portion from the source and drain regions of the fin structure includes etching the second semiconductor material portion to form the trench in the source and drain regions of the fin structure; and

the forming the third material portion in the source and drain regions includes epitaxially growing a semiconductor material in the trench.

7. The method of claim 6 further including tuning the etching and epitaxial growing to achieve strain for an NMOS fin-like field effect transistor (FinFET) device or a PMOS FinFET device.

8. The method of claim 7 wherein the tuning the etching to achieve strain for the NMOS FinFET device includes controlling the etching to partially remove the second semiconductor material portion from the source and drain regions of the fin structure.

9. The method of claim 7 wherein the tuning the etching to achieve strain for the PMOS FinFET device includes controlling the etching to completely remove the second semiconductor material portion from the source and drain regions of the fin structure.

10. A method comprising:

providing a semiconductor substrate;

forming a first fin structure and a second fin structure over the semiconductor substrate, the first and second fin structures including a first material portion and a second material portion, wherein the first and second fin structures each include a source region, a drain region, and a channel defined between the source and drain regions;

forming a first trench in the source and drain regions of the first fin structure;

forming a second trench in the source and drain regions of the second fin structure, wherein the forming the second trench in the source and drain regions of the second fin structure includes partially removing the second material portion from the source and drain regions of the second fin structure;

forming a third material portion in the first trench of the first fin structure; and

forming a fourth material portion in the second trench of the second fin structure, wherein the forming the fourth material portion in the second trench includes epitaxially growing a semiconductor material over a remaining second material portion.

11. The method of claim 10 wherein the forming the first trench in the source and drain regions of the first fin structure includes completely removing the second material portion from source and drain regions of the first fin structure, thereby exposing the first material portion in the source and drain regions of the first fin structure.

12. The method of claim 11 wherein the forming the third material portion in the first trench includes epitaxially growing a semiconductor material over the exposed first material portion.

13. The method of claim 10 wherein the forming the third and fourth material portions in the first and second trenches includes simultaneously epitaxially growing a semiconductor material in the first and second trenches.

19. The method of claim 10 wherein the second trench has a depth different than the first trench.

14. A method comprising:

forming a fin over a semiconductor substrate and at least partially embedded within a dielectric layer, the fin including a first semiconductor material portion disposed over the semiconductor substrate and a second semiconductor material portion disposed over the first semiconductor material portion;

forming a gate structure over the fin, such that the gate structure traverses the fin, thereby separating a source region and a drain region of the fin, wherein the source and drain regions of the fin define a channel region therebetween;

removing the second semiconductor material portion from the source and drain regions of the fin to form a trench extending below a top surface of the dielectric layer in the source and drain regions of the fin; and

forming a third semiconductor material portion in the source and drain regions of the fin.

15. The method of claim 14 wherein:

the removing the second conductive material portion from the source and drain regions of the fin includes partially etching the second semiconductor material portion; and

the forming the third conductive material portion in the source and drain regions of the fin includes epitaxially growing the third semiconductor material portion over a remaining second material portion.

16. The method of claim 14 wherein:

the removing the second semiconductor material portion from the source and drain regions of the fin includes completely etching the second semiconductor material portion to expose the first semiconductor material portion; and

the forming the third semiconductor material portion in the source and drain regions of the fin includes epitaxially growing the third semiconductor material portion over the exposed first semiconductor material portion.

17. The method of claim 14 further including:

forming another fin over the semiconductor substrate, the another fin including another first semiconductor material portion disposed over the semiconductor substrate and another second semiconductor material portion disposed over the another first semiconductor material portion;

forming another gate structure over the another fin, such that the another gate structure traverses the another fin, thereby separating a source region and a drain region of the another fin, wherein the source and drain regions of the another fin define a channel region therebetween;

removing the another second semiconductor material portion from the source and drain regions of the another fin; and

forming a fourth semiconductor material portion in the source and drain regions of the another fin.

18. The method of claim 17 further including simultaneously removing the second semiconductor material portion and the another second semiconductor material portion respectively from the source and drain regions of the fin and the another fin, wherein the second semiconductor material portion is completely removed from the source and drain regions of the fin and the another semiconductor second material portion is partially removed from the source and drain regions of the another fin.