Partitioned through-layer via and associated systems and methods

• US 8,367,538 B2
• Filed: 10/06/2010
• Issued: 02/05/2013
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Teck Kheng
• Primary Examiner(s): Wagner, Jenny L
• Application Number:
  US12/898,891
• Publication Number:
  US 20110019372A1
• Time in Patent Office: 853 Days
• Field of Search: 438/612, 438/620, 438/622
• US Class Current: 438/612
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 13/00 Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/09645 Patterning on via walls; Plural lands around one hole
• CPC Class Codes: H05K 2201/09854 Hole or via having special cross-section, e.g. elliptical
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: Y10T 29/49147 Assembling terminal to base

Abstract

Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.

Claims

1. A method for manufacturing a substrate, the method comprising:

forming a hole through a non-conductive layer, the hole including a sidewall;

after forming the hole, depositing a conductive layer on at least a portion of the sidewall and at least one of a top-side and a bottom-side of the non-conductive layer; and

forming partitions within the hole that separate the conductive layer into a first interconnect within the hole and a second interconnect within the hole that is electrically isolated form the first interconnect.

2. The method of claim 1 wherein the non-conductive layer comprises at least one of a dielectric core layer of a circuit board and a semiconductor layer of a semiconductor wafer.

3. The method of claim 1 wherein forming the hole and the partitions comprises removing conductive material from the conductive layer using a patterning process that includes at least one of chemical etching, mechanical drilling, laser drilling, and mechanical stamping.

4. The method of claim 1, further comprising at least partially filling the hole with a dielectric spacer material.

5. The method of claim 1 further comprising:

forming a lead land on at least one of a top-side portion and a bottom-side portion of the conductive layer, the lead land at least partially surrounding the hole and including first and second segmented portions, the first segmented portion being electrically coupled to the first interconnect and the second segmented portion being electrically coupled to the second interconnect and electrically isolated from the first interconnect.

6. The method of claim 5 further comprising forming a first trace on at least one of the top-side and bottom-side portions of the conductive layer, the first trace being electrically coupled to the first segmented portion of the lead land.

7. The method of claim 6 further comprising forming a second trace on at least one of the top-side and bottom-side portions of the conductive layer, the second trace being electrically coupled to the second segmented portion of the lead land.

8. The method of claim 7 wherein the first and second traces are located on the same side of the non-conductive layer and are substantially parallel to one another.

9. The method of claim 1 wherein forming the hole further includes forming the hole through a portion of a stacking layer that is attached to the non-conductive layer.

10. A method for manufacturing a substrate, the method comprising:

forming a via hole through a non-conductive material having a first side opposite a second side, the via hole including a sidewall extending between the first side and the second side;

after forming the hole, depositing a conductive material on at least a portion of the sidewall, the first side, and the second side of the non-conductive material;

forming partitions within the via hole that separate the conductive material into a first interconnect and a second interconnect within the via hole, the first and second interconnects being electrically isolated from each other; and

patterning the conductive material on the first and second sides of the non-conductive material to form

first and second lead lands electrically isolated from each other and in direct contact with the first and second interconnects, respectively; and

first and second traces in electrical contact with and extending away from the first and second lead lands, respectively.

11. The method of claim 10 wherein the non-conductive layer comprises at least one of a dielectric core layer of a circuit board and a semiconductor layer of a semiconductor wafer.

12. The method of claim 10 wherein forming the via hole and the partitions comprises removing a portion of the conductive material using a patterning process that includes at least one of chemical etching, mechanical drilling, laser drilling, and mechanical stamping.

13. The method of claim 10, further comprising at least partially filling the hole with a dielectric spacer material.

14. The method of claim 10, further comprising forming third and fourth lead lands on the second side of the non-conductive material, the third lead land being electrically coupled to the first interconnect and the fourth lead land being electrically coupled to the second interconnect.