Oxide semiconductor device with oxide semiconductor layers of different oxygen concentrations and method of manufacturing the same

• US 8,368,067 B2
• Filed: 12/08/2009
• Issued: 02/05/2013
• Est. Priority Date: 12/09/2008
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Uchiyama, Hiroyuki, Kawamura, Tetsufumi, Wakana, Hironori
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US12/633,577
• Publication Number:
  US 20100140614A1
• Time in Patent Office: 1,155 Days
• Field of Search: 257/43, 257/59, 257/72, 257/103, 257/E29.273, 257/E29.296
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02617 Deposition types
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10K 50/81 Anodes
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/80517 Multilayers, e.g. transparent multilayers

Abstract

A phenomenon of change of a contact resistance between an oxide semiconductor and a metal depending on an oxygen content ratio in introduced gas upon depositing an oxide semiconductor film made of indium gallium zinc oxide, zinc tin oxide, or others in an oxide semiconductor thin-film transistor. A contact layer is formed with an oxygen content ratio of 10% or higher in a region from a surface, where the metal and the oxide semiconductor are contacted, down to at least 3 nm deep in depth direction, and a region to be a main channel layer is further formed with an oxygen content ratio of 10% or lower, so that a multilayered structure is formed, and both of ohmic characteristics to the electrode metal and reliability such as the suppression of threshold potential shift are achieved.

Claims

1. An oxide semiconductor device comprising an oxide semiconductor layer and first and second electrodes contacting a first surface of the oxide semiconductor layer,

wherein the oxide semiconductor layer includes:

a first layer having a substantially uniform first oxygen-content concentration; and

a second layer provided between the first and second electrodes and the first layer such that an upper surface of the second layer contacts bottom surfaces of the first and second electrodes, and having a substantially uniform second oxygen-content concentration, and

wherein the second oxygen-content concentration is higher than the first oxygen-content concentration.

2. The oxide semiconductor device according to claim 1, wherein

the second layer has a thickness of 3 nm or larger.

3. The oxide semiconductor device according to claim 1, wherein

the second oxygen-content concentration is 10²¹ atomic concentration or higher, and

the first oxygen-content concentration is below 10²¹ atomic concentration.

4. The oxide semiconductor device according to claim 1, wherein

there is a 10 times or more difference between the first oxygen-content concentration and the second oxygen-content concentration.

5. The oxide semiconductor device according to claim 1, wherein

the oxide semiconductor layer includes one of zinc oxide (ZnO), indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and zinc indium oxide (ZIO).

6. The oxide semiconductor device according to claim 1, wherein

a third layer, in which a difference in the oxygen concentrations relative to the first layer and the second layer is gradedly decreased, is provided between the first layer and the second layer.

7. The oxide semiconductor device according to claim 1, wherein

a layer having a substantially uniform oxygen-content concentration within a range of the oxygen-content concentration of the first layer and the oxygen-content concentration of the second layer is provided between the first layer and the second layer.

8. The oxide semiconductor device according to claim 1, wherein

each of the first and second electrodes comprises a plurality of layers including a transparent conductive film contacting the oxide semiconductor layer, the transparent conductive film having a lower conductivity than a conductivity of a second layer of the first and second electrodes not contacting the oxide semiconductor layer.

9. The oxide semiconductor device according to claim 1, wherein

a transistor of a bottom-gate top-contact type or a top-gate bottom-contact type is configured having:

a gate electrode provided on a second surface of the oxide semiconductor layer with an interposing gate insulating film; and

a source electrode and a drain electrode contacting the first surface of the oxide semiconductor layer.

10. An active matrix substrate including the oxide semiconductor device according to claim 9, wherein

a plurality of gate lines and a plurality of data lines are provided on a substrate, and

a transistor as aforesaid is arranged in each pixel arranged in the matrix at intersections of the plurality of gate lines and the plurality of data lines.

11. The oxide semiconductor device according to claim 1, wherein

a transistor of a top-gate top-contact type or a bottom-gate bottom-contact type is configured having:

a gate electrode provided on a second surface of the oxide semiconductor layer with an interposing gate insulating film; and

a source electrode and a drain electrode contacting the first surface of the oxide semiconductor layer.

12. An active matrix substrate including the oxide semiconductor device according to claim 11, wherein

a plurality of gate lines and a plurality of data lines are provided on a substrate, and

a transistor as aforesaid is arranged in each pixel arranged in the matrix at intersections of the plurality of gate lines and the plurality of data lines.