Trench metal oxide semiconductor with recessed trench material and remote contacts

• US 8,368,126 B2
• Filed: 04/07/2008
• Issued: 02/05/2013
• Est. Priority Date: 04/19/2007
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Pattanayak, Deva N., Terrill, Kyle, Shi, Sharon, Lee, Misha, Bai, Yuming, Lui, Kam, Chen, Kuo-In
• Primary Examiner(s): LOUIE, WAI SING
• Application Number:
  US12/098,950
• Publication Number:
  US 20080258212A1
• Time in Patent Office: 1,765 Days
• Field of Search: 257/331, 257/355, 257/E21.91, 257/260, 257/280, 257/284, 438/272
• US Class Current: 257/260
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.

Claims

1. A semiconductor device comprising a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, said TMBS device comprising:

a substrate having formed therein a plurality of first trenches, wherein a conductive material is deposited in said first trenches;

said TMBS device having an active region comprising regions between said first trenches; and

a source metal layer formed over said regions and over said first trenches, wherein, within said active region, said source metal layer is in electrical contact with said substrate but is isolated from said conductive material disposed within said first trenches, wherein said conductive material within said first trenches is electrically coupled to a contact that is outside of said active region of said TMBS device.

2. The semiconductor device of claim 1 wherein said active region comprises a plurality of mesas formed between said first trenches, said mesas having sidewalls of a first height, wherein said conductive material fills said first trenches to a second height that is less than said first height.

3. The semiconductor device of claim 2 wherein said conductive material extends through said substrate, said conductive material also extending outside said active region of said TMBS device and to said contact.

4. The semiconductor device of claim 1 further comprising insulating material separating said conductive material from said substrate and from said source metal layer.

5. The semiconductor device of claim 4 wherein said insulating material comprises a gate oxide.

6. The semiconductor device of claim 1 wherein said substrate comprises a p-type silicon substrate and said conductive material comprises polysilicon.

7. The semiconductor device of claim 1 wherein said source metal layer comprises a material selected from the group consisting of:

titanium nitride, titanium, and aluminum.

8. The semiconductor device of claim 1 further comprising a metal oxide semiconductor field electrical transistor (MOSFET), said MOSFET and said TMBS device in combination comprising a monolithically integrated structure.

9. The semiconductor device of claim 8 wherein said MOSFET comprises:

a plurality of second trenches formed within said substrate and having said conductive material disposed therein; and

source implants adjacent to each of said second trenches but separated from said conductive material in said second trenches by said insulating material;

said MOSFET having an active region in which said source metal layer is disposed over said second trenches and is in electrical contact with a p-body implant formed in said substrate between said second trenches, wherein electrical contact between said conductive material in said second trenches and a gate metal is made outside of said active region of said MOSFET.

10. A semiconductor device comprising a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, said TMBS device comprising:

a substrate having formed therein a plurality of mesas having sidewalls of a first height;

conductive material disposed within a plurality of first trenches located between said mesas, said conductive material filling said first trenches to a second height that is less than said first height; and

insulating material separating said conductive material inside said first trenches from said substrate and from a source metal layer disposed over said mesas and said first trenches;

wherein said source metal layer is in electrical contact with said mesas within an active region of said TMBS device, wherein said active region comprises regions between said first trenches, wherein electrical contact between said conductive material in said first trenches and said source metal layer is made outside of said active region of said TMBS device.

11. The semiconductor device of claim 10 wherein said insulating material comprises a gate oxide, said substrate comprises a p-type silicon substrate, said conductive material comprises polysilicon, and said source metal layer comprises a material selected from the group consisting of:

titanium nitride, titanium, and aluminum.

12. The semiconductor device of claim 10 further comprising a metal oxide semiconductor field electrical transistor (MOSFET) formed on said substrate, said MOSFET and said TMBS in combination comprising a monolithically integrated structure.

13. The semiconductor device of claim 12 wherein said MOSFET comprises a plurality of second trenches formed within said substrate and having said conductive material disposed therein;

wherein, within an active region of said MOSFET, said source metal layer is disposed over said second trenches and over p-body implants formed in said substrate between said second trenches, wherein electrical contact between said conductive material in said second trenches and a gate metal is made outside of said active region of said MOSFET, and wherein said source metal layer is in electrical contact with said p-body implants but not with said conductive material in said second trenches.

14. The semiconductor device of claim 13 further comprising source implants adjacent to each of said second trenches but separated from said conductive material in said second trenches by said insulating material.

15. The semiconductor device of claim 13 further comprising a dielectric layer disposed over said second trenches but separated by gaps allowing said electrical contact between said source metal layer and said p-body implants.

16. The semiconductor device of claim 15 wherein said dielectric layer comprises a dielectric stack comprising a layer of tetraethylorthosilicate (TEOS) and a layer of borophosphosilicate glass (BPSG).

17. The semiconductor device of claim 10 wherein said conductive material extends through said substrate, to outside said active region of said TMBS device, and to an electrical contact that is outside said active region.