Semiconductor device and electronic device
First Claim
1. A semiconductor device comprising:
- a semiconductor region;
a first electrode;
a second electrode;
a third electrode electrically connected to the first electrode;
a fourth electrode electrically connected to the second electrode;
a fifth electrode electrically connected to the third electrode;
a sixth electrode electrically connected to the fourth electrode; and
a functional circuit,wherein the sixth electrode is provided over the semiconductor region,wherein the semiconductor region comprises;
a first impurity region comprising one of an n-type impurity and a p-type impurity;
a resistance region provided at an inner periphery portion of the first impurity region in a plane view; and
a second impurity region comprising the other of the n-type impurity and the p-type impurity and provided at an inner periphery portion of the resistance region in the plane view,wherein the first impurity region is electrically connected to the first electrode,wherein the second impurity region is electrically connected to the second electrode,wherein a first terminal of the functional circuit is electrically connected to the first electrode, andwherein a second terminal of the functional circuit is electrically connected to the second electrode.
1 Assignment
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Accused Products
Abstract
A semiconductor device has a structure including the first semiconductor region 103 which is provided in the first terminal portion 100 and includes the first n-type impurity region 106, the first resistance region 107 provided at an inner periphery portion of the first n-type impurity region 106 in a plane view, and the first p-type impurity region 108 provided at an inner periphery portion of the first resistance region 107 in the plane view, and the second semiconductor region 104 which is provided in the second terminal portion 101 and includes the second p-type impurity region 109, the second resistance region 110 provided at an inner periphery portion of the second p-type impurity region 109 in the plane view, and the second n-type impurity region 111 provided at an inner periphery portion of the second resistance region 110 in the plane view.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a semiconductor region; a first electrode; a second electrode; a third electrode electrically connected to the first electrode; a fourth electrode electrically connected to the second electrode; a fifth electrode electrically connected to the third electrode; a sixth electrode electrically connected to the fourth electrode; and a functional circuit, wherein the sixth electrode is provided over the semiconductor region, wherein the semiconductor region comprises; a first impurity region comprising one of an n-type impurity and a p-type impurity; a resistance region provided at an inner periphery portion of the first impurity region in a plane view; and a second impurity region comprising the other of the n-type impurity and the p-type impurity and provided at an inner periphery portion of the resistance region in the plane view, wherein the first impurity region is electrically connected to the first electrode, wherein the second impurity region is electrically connected to the second electrode, wherein a first terminal of the functional circuit is electrically connected to the first electrode, and wherein a second terminal of the functional circuit is electrically connected to the second electrode. - View Dependent Claims (2, 3, 4, 5, 6, 18)
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7. A semiconductor device comprising:
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a substrate; a semiconductor region formed over the substrate; a first electrode; a second electrode; a third electrode electrically connected to the first electrode; a fourth electrode electrically connected to the second electrode; a fifth electrode electrically connected to the third electrode; a sixth electrode electrically connected to the fourth electrode; and a functional circuit, wherein the sixth electrode is provided over the semiconductor region, wherein the semiconductor region comprises; a first impurity region comprising one of an n-type impurity and a p-type impurity; a resistance region provided at an inner periphery portion of the first impurity region in a plane view; and a second impurity region comprising the other of the n-type impurity and the p-type impurity and provided at an inner periphery portion of the resistance region in the plane view, wherein the first impurity region is electrically connected to the first electrode, wherein the second impurity region is electrically connected to the second electrode, wherein a first terminal of the functional circuit is electrically connected to the first electrode, and wherein a second terminal of the functional circuit is electrically connected to the second electrode. - View Dependent Claims (8, 9, 10, 11, 12, 19)
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13. A semiconductor device comprising:
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a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; a third electrode; a fourth electrode; a fifth electrode electrically connected to the second electrode and the third electrode; a sixth electrode electrically connected to the first electrode and the fourth electrode; a seventh electrode electrically connected to the fifth electrode; and a eighth electrode electrically connected to the sixth electrode, a functional circuit, wherein the seventh electrode is provided over the first semiconductor region, wherein the eighth electrode is provided over the second semiconductor region, wherein the first semiconductor region comprises; a first n-type impurity region in contact with the first electrode; a first resistance region provided at an inner periphery portion of the first n-type impurity region in a plane view; and a first p-type impurity region provided at an inner periphery portion of the first resistance region in the plane view and in contact with the second electrode, and wherein the second semiconductor region comprises; a second p-type impurity region in contact with the third electrode; a second resistance region provided at an inner periphery portion of the second p-type impurity region in the plane view; and a second n-type impurity region provided at an inner periphery portion of the second resistance region in the plane view and in contact with the fourth electrode, wherein the seventh electrode overlaps with the first n-type impurity region, the first resistance region, and the first p-type impurity region, wherein the eighth electrode overlaps with the second n-type impurity region, the second resistance region, and the second p-type impurity region, wherein a first terminal of the functional circuit is electrically connected to the first electrode, and wherein a second terminal of the functional circuit is electrically connected to the second electrode. - View Dependent Claims (14, 15, 16, 17, 20)
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Specification