Semiconductor device having a device isolation structure

• US 8,368,169 B2
• Filed: 10/04/2010
• Issued: 02/05/2013
• Est. Priority Date: 11/12/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Han, Seunguk, Yamada, Satoru, Choi, Young Jin
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US12/897,095
• Publication Number:
  US 20110108962A1
• Time in Patent Office: 855 Days
• Field of Search: 257/E21.54, 257/E21.545, 257/E21.546, 257/499, 257/506, 257/632, 257/635, 257/637, 438/424, 438/430, 438/434, 438/435
• US Class Current: 257/506
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

An example semiconductor device includes a trench formed in a semiconductor substrate to define an active region, a filling dielectric layer provided within the trench, an oxide layer provided between the filling dielectric layer and the trench, a nitride layer provided between the oxide layer and the filling dielectric layer, and a barrier layer provided between the oxide layer and the nitride layer.

Claims

1. A semiconductor device having a device isolation structure, comprising:

a trench formed in a semiconductor substrate to define an active region, the semiconductor substrate including an NMOS region and a PMOS region;

a filling dielectric layer provided within the trench;

an oxide layer provided between the filling dielectric layer and the trench;

a nitride layer provided between the oxide layer and the filling dielectric layer;

an inner wall of the trench in the NMOS region is covered with the oxide layer and the nitride layer;

an inner wall of the trench in the PMOS region is covered with the oxide layer, the nitride layer, and a barrier layer provided between the oxide layer and the nitride layer; and

the nitride layer is in direct contact with the oxide layer in the NMOS region.

2. The semiconductor device claim 1, wherein the barrier layer comprises one of undoped polysilicon, doped polysilicon, and metal.

3. The semiconductor device of claim 1, wherein a thickness of the barrier layer is less than a thickness of the nitride layer.

4. The semiconductor device of claim 1, wherein the barrier layer is conformally provided on a sidewall portion and a bottom portion of the trench.

5. The semiconductor device of claim 1, wherein the barrier layer is provided on a sidewall portion of the trench and the nitride layer is in direct contact with the oxide layer at a bottom portion of the trench.

6. The semiconductor device of claim 1, wherein the nitride layer is in contact with the oxide layer at an upper portion of the trench.

7. The semiconductor device of claim 1, further comprising:

a buffer insulating layer covering an upper surface of the barrier layer at an upper portion of the trench.

8. The semiconductor device of claim 7, wherein the buffer insulating layer is provided between the oxide layer and the nitride layer.

9. The semiconductor device of claim 1, wherein the buffer insulating layer is provided between the oxide layer and the filling insulating layer.

10. The semiconductor device of claim 1, wherein a distance between an uppermost surface of the barrier layer and an upper surface of the semiconductor substrate is greater than a thickness of the oxide layer.

11. The semiconductor device of claim 1, wherein a distance between an uppermost surface of the nitride layer and an upper surface of the semiconductor substrate is greater than a thickness of the oxide layer.

12. The semiconductor device of claim 1, further comprising:

a gate line crossing the active region on the semiconductor substrate;

impurity regions at both sides of the gate line; and

the barrier layer comprising a doped polysilicon layer having an opposite conductivity type to the impurity regions.