Chip package

• US 8,368,193 B2
• Filed: 09/19/2011
• Issued: 02/05/2013
• Est. Priority Date: 06/06/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lin, Shih-Hsiung, Lo, Hsin-Jung
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US13/236,507
• Publication Number:
  US 20120007237A1
• Time in Patent Office: 505 Days
• Field of Search: 257432-436, 257/680, 257/E23.009, 257/E23.01, 257/E23.011, 438/69, 438/70, 438/116, 438/121
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 31/0203 Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.

Claims

1. A circuit component comprising:

a semiconductor chip comprising multiple transistors, a passivation layer over said multiple transistors, wherein said passivation layer comprises a nitride layer, and a metal pad having a contact point at a bottom of an opening in said passivation layer, wherein said opening is over said contact point;

a flexible substrate;

a first metal bump between said contact point and a metal trace of said flexible substrate, wherein said first metal bump is connected to said contact point through said opening, wherein said metal trace of said flexible substrate is connected to said contact point through said first metal bump, wherein said first metal bump comprises a first copper layer having a thickness between 5 and 50 micrometers;

a substrate component comprising a glass substrate; and

a polymer over said flexible substrate, wherein said polymer joins said metal trace and joins said substrate component.

2. The circuit component of claim 1 further comprising a second metal bump joining said substrate component, wherein said second metal bump comprises a gold layer having a thickness between 1000 angstroms and 2 micrometers.

3. The circuit component of claim 1 further comprising a second metal bump joining said substrate component, wherein said second metal bump comprises a gold layer having a thickness between 1 and 50 micrometers.

4. The circuit component of claim 1 further comprising a second metal bump joining said substrate component, wherein said second metal bump comprises a second copper layer having a thickness between 5 and 50 micrometers.

5. The circuit component of claim 1 further comprising a second metal bump joining said substrate component, wherein said second metal bump comprises a nickel layer having a thickness between 1 and 100 micrometers.

6. The circuit component of claim 1, wherein said first metal bump further comprises a titanium-containing layer under said first copper layer.

7. The circuit component of claim 1, wherein said first metal bump further comprises a tin-containing solder at a top of said metal bump.

8. The circuit component of claim 7, wherein said tin-containing solder comprises silver.

9. The circuit component of claim 1, wherein said first metal bump further comprises a nickel-containing layer on said first copper layer.

10. The circuit component of claim 9, wherein said nickel-containing layer has a thickness between 1 and 100 micrometers.

11. A circuit component comprising:

a semiconductor chip comprising multiple transistors, a passivation layer over said multiple transistors, wherein said passivation layer comprises a nitride layer, and a metal pad having a contact point at a bottom of an opening in said passivation layer, wherein said opening is over said contact point;

a substrate component comprising a glass substrate over said semiconductor chip;

a first metal bump between said contact point and said glass substrate, wherein said first metal bump is connected to said contact point through said opening, wherein said first metal bump comprises a first copper layer having a thickness between 5 and 50 micrometers;

a flexible substrate; and

a polymer joining said substrate component and joining a metal trace of said flexible substrate.

12. The circuit component of claim 11 further comprising a second metal bump joining said flexible substrate, wherein said second metal bump comprises a gold layer having a thickness between 1000 angstroms and 2 micrometers.

13. The circuit component of claim 11 further comprising a second metal bump joining said flexible substrate, wherein said second metal bump comprises a gold layer having a thickness between 1 and 50 micrometers.

14. The circuit component of claim 11 further comprising a second metal bump joining said flexible substrate, wherein said second metal bump comprises a second copper layer having a thickness between 5 and 50 micrometers.

15. The circuit component of claim 11 further comprising a second metal bump joining said flexible substrate, wherein said second metal bump comprises a nickel layer having a thickness between 1 and 100 micrometers.

16. The circuit component of claim 11, wherein said first metal bump further comprises a titanium-containing layer under said first copper layer.

17. The circuit component of claim 11, wherein said first metal bump further comprises a tin-containing solder at a top of said first metal bump.

18. The circuit component of claim 17, wherein said tin-containing solder comprises silver.

19. The circuit component of claim 11, wherein said first metal bump further comprises a nickel-containing layer on said first copper layer.

20. The circuit component of claim 19, wherein said nickel-containing layer has a thickness between 1 and 100 micrometers.

21. A chip package comprising:

a semiconductor chip comprising multiple CMOS devices, an insulating layer over said multiple CMOS devices, a metal pad having a contact point under a first opening in said insulating layer, an optical filter over said insulating layer and said multiple CMOS devices, and multiple microlenses over said optical filter, said insulating layer and said multiple CMOS devices;

a circuit component joining said semiconductor chip, wherein a second opening through said circuit component is vertically over said semiconductor chip;

a metal bump between said circuit component and said contact point, wherein said metal bump has a bottom end joining said contact point and a top end joining said circuit component, wherein said metal bump comprises gold; and

a transparent substrate over said semiconductor chip, said multiple microlenses and said optical filter, wherein a cell is between said semiconductor chip and said transparent substrate and vertically over a photo-sensitive area of said semiconductor chip.

22. The chip package of claim 21, wherein said transparent substrate comprises a glass substrate.

23. The chip package of claim 21 further comprising a spacer between said semiconductor chip and said transparent substrate.

24. The chip package of claim 23, wherein said spacer comprises a polymer.

25. The chip package of claim 21, wherein said insulating layer comprises an oxide layer.

26. The chip package of claim 25, wherein said oxide layer has a thickness between 0.2 and 0.7 micrometers.

27. The chip package of claim 21, wherein said metal pad comprises a copper layer.

28. The chip package of claim 21, wherein said metal pad comprises aluminum.

29. A circuit component comprising:

a first substrate;

a second substrate over said first substrate;

a flexible substrate connected to said first substrate; and

a first metal bump between said first and second substrates, wherein said first metal bump comprises a first copper layer having a thickness between 5 and 50 micrometers.

30. The circuit component of claim 29 further comprising a second metal bump between said flexible substrate and said first substrate, wherein said second metal bump comprises a gold layer having a thickness between 1000 angstroms and 2 micrometers.

31. The circuit component of claim 29 further comprising a second metal bump between said flexible substrate and said first substrate, wherein said second metal bump comprises a gold layer having a thickness between 1 and 50 micrometers.

32. The circuit component of claim 29 further comprising a second metal bump between said flexible substrate and said first substrate, wherein said second metal bump comprises a second copper layer having a thickness between 5 and 50 micrometers.

33. The circuit component of claim 29 further comprising a second metal bump between said flexible substrate and said first substrate, wherein said second metal bump comprises a nickel layer having a thickness between 1 and 100 micrometers.

34. The circuit component of claim 29, wherein said first metal bump further comprises a titanium-containing layer under said first copper layer.

35. The circuit component of claim 29, wherein said first metal bump further comprises a tin-containing solder at a top of said first metal bump.

36. The circuit component of claim 35, wherein said tin-containing solder comprises silver.

37. The circuit component of claim 29, wherein said first metal bump further comprises a nickel-containing layer on said copper layer.

38. The circuit component of claim 37, wherein said nickel-containing layer has a thickness between 1 and 100 micrometers.

39. The circuit component of claim 29, wherein said second substrate comprises a glass substrate.