Chip structure and process for forming the same

• US 8,368,204 B2
• Filed: 10/19/2011
• Issued: 02/05/2013
• Est. Priority Date: 12/21/1998
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US13/277,142
• Publication Number:
  US 20120098128A1
• Time in Patent Office: 475 Days
• Field of Search: 257/700, 257/758, 257/E23.167
• US Class Current: 257/700
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.

Claims

1. A chip comprising:

a silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first copper layer, a second copper layer over said first copper layer and a copper plug between said first and second copper layers, wherein said second copper layer is connected to said first copper layer through said copper plug;

a first dielectric layer over said silicon substrate, wherein said first dielectric layer comprises a portion between said first and second copper layers, wherein said copper plug is in said first dielectric layer;

an insulating layer over said silicon substrate and over said metallization structure, wherein a first opening in said insulating layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said insulating layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening;

a first circuit layer over said insulating layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said first circuit layer, wherein said first circuit layer comprises a first trace portion, a first via portion between said first trace portion and said first contact point and a second via portion between said first trace portion and said second contact point, wherein said first trace portion has a thickness greater than 1 micrometer, wherein said first circuit layer comprises a third copper layer and a first conductive layer under said third copper layer and at a sidewall of said first trace portion;

a second circuit layer over said first circuit layer and said insulating layer, wherein said second circuit layer comprises a second trace portion, a third via portion at a bottom of said second trace portion, wherein said second trace portion has a thickness greater than 1 micrometer, wherein said second circuit layer comprises a fourth copper layer and a second conductive layer under said fourth copper layer and at a sidewall of said second trace portion; and

a second dielectric layer over said insulating layer, wherein said second dielectric layer comprises a portion between said first and second circuit layers.

2. The chip of claim 1, wherein said insulating layer comprises a nitride.

3. The chip of claim 1, wherein said insulating layer comprises an oxide.

4. The chip of claim 1, wherein said first dielectric layer comprises an oxide.

5. The chip of claim 1, wherein said third via portion has a cross-sectional area greater than 1 square micrometers.

6. The chip of claim 1, wherein said third via portion has a bottom contacting said first circuit layer, wherein said second trace portion is connected to said first contact point through said first via portion, wherein said second trace portion is connected to said second contact point through said second via portion.

7. The chip of claim 1, wherein said first trace portion extends in a same direction as said second trace portion extends.

8. The chip of claim 1 further comprising a third dielectric layer on said second circuit layer and over said second dielectric layer, wherein a third opening in said third dielectric layer is over a third contact point of said second circuit layer, and said third contact point is at a bottom of said third opening.

9. The chip of claim 8, wherein said third dielectric layer is further vertically over said first, second and third via portions.

10. The chip of claim 8, wherein said third dielectric layer comprises an organic material.

11. The chip of claim 1, wherein said third via portion is vertically over said first via portion.

12. The chip of claim 1, wherein said third contact point is configured to be connected to a bump for external connection through said third opening.

13. The chip of claim 1, wherein said third contact point is configured to be connected to a conductive wire for external connection through said third opening.

14. The chip of claim 1, wherein said first conductive layer comprises titanium.

15. The chip of claim 1, wherein said second conductive layer comprises titanium.

16. The chip of claim 1, wherein said first circuit layer comprises a ground interconnect.

17. The chip of claim 1, wherein said second dielectric layer comprises an organic material.

18. A chip comprising:

a silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first copper layer, a second copper layer over said first copper layer and a copper plug between said first and second copper layers, wherein said second copper layer is connected to said first copper layer through said copper plug;

a first dielectric layer over said silicon substrate, wherein said first dielectric layer comprises a portion between said first and second copper layers, wherein said copper plug is in said first dielectric layer;

a passivation layer over said silicon substrate and over said metallization structure, wherein said passivation layer comprises a nitride, wherein a first opening in said passivation layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, wherein a second opening in said passivation layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening;

a first circuit layer over said passivation layer and on said first and second contact points, wherein said first contact point is connected to said second contact point through said first circuit layer, wherein said first circuit layer comprises a first trace portion, a first via portion between said first trace portion and said first contact point and a second via portion between said first trace portion and said second contact point, wherein said first circuit layer comprises a third copper layer and a first conductive layer under said third copper layer and at a sidewall of said first trace portion;

a second circuit layer over said first circuit layer and said passivation layer, wherein said second circuit layer comprises a second trace portion, a third via portion at a bottom of said second trace portion, wherein said second circuit layer comprises a fourth copper layer and a second conductive layer under said fourth copper layer and at a sidewall of said second trace portion; and

a second dielectric layer over said passivation layer, wherein said second dielectric layer comprises a portion between said first and second circuit layers.

19. The chip of claim 18, wherein said first trace portion has a thickness greater than 1 micrometer.

20. The chip of claim 18, wherein said second trace portion has a thickness greater than 1 micrometer.

21. The chip of claim 18, wherein said third via portion has a cross-sectional area greater than 1 square micrometers.

22. The chip of claim 18, wherein said third via portion has a bottom contacting said first circuit layer, wherein said second trace portion is connected to said first contact point through said first via portion, wherein said second trace portion is connected to said second contact point through said second via portion.

23. The chip of claim 18, wherein said first trace portion extends in a same direction as said second trace portion extends.

24. The chip of claim 18, further comprising a third dielectric layer on said second circuit layer and over said second dielectric layer, wherein a third opening in said third dielectric layer is over a third contact point of said second circuit layer, and said third contact point is at a bottom of said third opening.

25. The chip of claim 24, wherein said third dielectric layer is further vertically over said first, second and third via portions.

26. The chip of claim 24, wherein said third dielectric layer comprises an organic material.

27. The chip of claim 18, wherein said third via portion is vertically over said first via portion.

28. The chip of claim 18, wherein said third contact point is configured to be connected to a bump for external connection through said third opening.

29. The chip of claim 18, wherein said third contact point is configured to be connected to a conductive wire for external connection through said third opening.

30. The chip of claim 18, wherein said first conductive layer comprises titanium.

31. The chip of claim 18, wherein said second conductive layer comprises titanium.

32. The chip of claim 18, wherein said first circuit layer comprises a ground interconnect.

33. The chip of claim 18, wherein said second dielectric layer comprises an organic material.