Low fabrication cost, fine pitch and high reliability solder bump

• US 8,368,213 B2
• Filed: 09/07/2004
• Issued: 02/05/2013
• Est. Priority Date: 03/05/2001
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Lin, Mou-Shiung, Huang, Ching-Cheng
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): SHOOK, DANIEL P
• Application Number:
  US10/935,451
• Publication Number:
  US 20050032349A1
• Time in Patent Office: 3,073 Days
• Field of Search: 257/751, 257/773, 257/748, 257/772, 257/775, 257/781, 257/786, 257/750, 257/763, 257/764, 257/753, 257/673, 257736-738, 257E23012-E23022, 438/614, 438/FOR.343, 438/656, 438/666, 438/611, 438/612, 438652-654, 438/672, 438/675, 228/180.22
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Claims

1. An integrated circuit device comprising:

a silicon substrate;

multiple layers of interconnecting lines;

multiple insulating layers comprising an oxide;

multiple metal vias in said multiple insulating layers and between said multiple layers of interconnecting lines, wherein said multiple metal vias are connected to said multiple layers of interconnecting lines;

a polymer layer over said silicon substrate, wherein an opening in said polymer layer is over a contact point of said multiple layers of interconnecting lines; and

a metal bump on said contact point and on a top surface of said polymer layer, wherein said metal bump is connected to said contact point through said opening, wherein said metal bump comprises a metal layer on said contact point and on said top surface of said polymer layer, a copper pillar on said metal layer, wherein said copper pillar has a thickness between 10 micrometers and 100 micrometers, a nickel-containing layer on said copper pillar, wherein said nickel-containing layer has a width greater than said thickness of said copper pillar, and a spherical-contoured solder bump on said nickel-containing layer, wherein a left edge of said spherical-contoured solder bump extends further than a left edge of said nickel-containing layer and wherein a right edge of said semi-spherical contoured solder bump extends further than a right edge of said nickel-containing layer.

2. The integrated circuit device of claim 1, wherein said nickel-containing layer has a thickness between 1 micrometer and 10 micrometers.

3. The integrated circuit device of claim 1, wherein said metal layer comprises titanium.

4. The integrated circuit device of claim 1, wherein said polymer layer comprises polyimide.

5. The integrated circuit device of claim 1, wherein said multiple layers of interconnecting lines comprise aluminum.

6. The integrated circuit device of claim 1, wherein said multiple layers of interconnecting lines comprise copper.

7. The integrated circuit device of claim 1, wherein said metal layer comprises a titanium-containing layer having a thickness between 500 and 2000 angstroms.

8. The integrated circuit device of claim 1, wherein said copper pillar is electroplated.

9. The integrated circuit device of claim 1, wherein said metal layer comprises titanium nitride.

10. The integrated circuit device of claim 1, wherein said solder has a thickness between 30 and 100 micrometers.

11. The chip of claim 1, wherein said thickness of said copper pillar is greater than a width of said copper pillar.

12. A chip comprising:

a silicon substrate;

multiple layers of interconnecting lines;

multiple insulating layers comprising an oxide;

multiple metal vias in said multiple insulating layers and between said multiple layers of interconnecting lines, wherein said multiple metal vias are connected to said multiple layers of interconnecting lines;

a passivation layer over said silicon substrate, wherein an opening in said passivation layer is over a contact point of said multiple layers of interconnecting lines, and said contact point is at a bottom of said opening in said passivation layer, wherein said passivation layer comprises a nitride; and

a metal bump on said contact point and on a top surface of said passivation layer, wherein said metal bump comprises a metal layer on said contact point and on said top surface of said passivation layer, wherein said metal layer comprises a titanium-nitride layer on said contact point, a copper pillar on said metal layer, wherein said copper pillar has a thickness between 10 and 100 micrometers, a nickel-containing layer on said copper pillar, wherein said nickel-containing layer has a width greater than said thickness of said copper pillar, and a spherical-contoured solder bump on said nickel-containing layer, wherein a left edge of said spherical-contoured solder bump extends further than a left edge of said nickel-containing layer and wherein a right edge of said spherical-contoured solder bump extends further than a right edge of said nickel-containing layer.

13. The chip of claim 12, wherein said titanium-nitride layer has a thickness between 500 and 2,000 angstroms.

14. The chip of claim 12, wherein said copper pillar is electroplated.

15. The chip of claim 12, wherein said nickel-containing layer has a thickness between 1 and 10 micrometers.

16. The chip of claim 12, wherein said solder has a thickness between 30 and 100 micrometers.

17. The chip of claim 12, wherein said multiple layers of interconnecting lines comprise copper.

18. The chip of claim 12, wherein said multiple layers of interconnecting lines comprise aluminum.

19. The chip of claim 12, wherein said thickness of said copper pillar is greater than a width of said copper pillar.

20. A chip comprising:

a silicon substrate;

a metal contact pad over said silicon substrate;

an oxide-or-nitride-containing layer over said silicon substrate, wherein an opening in said oxide-or-nitride-containing layer is over said metal contact pad;

an aluminum-containing layer over said metal contact pad and said oxide-or-nitride-containing layer, wherein said aluminum-containing layer is connected to said metal contact pad through said opening, wherein said aluminum-containing layer has a top surface with a first region, a second region and a third region between said first and second regions, wherein said first and second regions are exposed;

a copper pillar vertically over said third region but not vertically over said first and second regions, wherein said copper pillar has a thickness of between 10 micrometers and 100 micrometers and

a nickel-containing layer on said copper pillar, wherein said nickel-containing layer has a width greater than said thickness of said copper pillar, and a spherical-contoured solder bump on said nickel-containing layer, wherein a left edge of said spherical-contoured solder bump extends further than a left edge of said nickel-containing layer and wherein a right edge of said spherical-contoured solder bump extends further than a right edge of said nickel-containing layer.

21. The chip of claim 20 further comprising a solder over said copper pillar.

22. The chip of claim 20 further comprising a nickel-containing layer over said copper pillar.

23. The chip of claim 20 further comprising a nickel layer on said copper pillar, wherein said nickel layer has a thickness between 1 and 10 micrometers.

24. The chip of claim 20, wherein said metal contact pad comprises aluminum.

25. The chip of claim 20, wherein said metal contact pad comprises copper.

26. The chip of claim 20, wherein said thickness of said copper pillar is greater than a width of said copper pillar.

27. A chip comprising:

a silicon substrate;

a metal contact pad over said silicon substrate;

an oxide-or-nitride-containing layer over said silicon substrate, wherein an opening in said oxide-or-nitride-containing layer is over said metal contact pad;

a metal layer over said metal contact pad and said oxide-or-nitride-containing layer, wherein said metal layer is connected to said metal contact pad through said opening, wherein said metal layer has a top surface with a first region, a second region and a third region between said first and second regions, wherein said first and second regions are exposed;

a copper pillar vertically over said third region but not vertically over said first and second regions, wherein said copper pillar has a thickness greater than a width of said opening; and

a nickel-containing layer on said copper pillar, wherein said nickel-containing layer has a width greater than said thickness of said copper pillar, and a spherical-contoured solder bump on said nickel-containing layer, wherein a left edge of said spherical-contoured solder bump extends further than a left edge of said nickel-containing layer and wherein a right edge of said spherical-contoured solder bump extends further than a right edge of said nickel-containing layer.

28. The chip of claim 27 further comprising a solder over said copper pillar.

29. The chip of claim 27 further comprising a nickel-containing layer over said copper pillar.

30. The chip of claim 27 further comprising a nickel layer on said copper pillar, wherein said nickel layer has a thickness between 1 and 10 micrometers.

31. The chip of claim 27, wherein said metal contact pad comprises aluminum.

32. The chip of claim 27, wherein said metal contact pad comprises copper.

33. The chip of claim 27, wherein said thickness of said copper pillar is between 10 and 100 micrometers.

34. The chip of claim 27, wherein said metal layer comprises aluminum.