Rectifier-free piezoelectric energy harverster and battery charger

• US 8,368,290 B2
• Filed: 05/18/2011
• Issued: 02/05/2013
• Est. Priority Date: 05/18/2010
• Status: Expired due to Fees

• Current Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Original Assignee: Georgia Tech Research Corporation (University System of Georgia)
• Inventors: Kwon, Dongwon, Rincon-Mora, Gabriel Alfonso
• Primary Examiner(s): Budd, Mark
• Application Number:
  US13/110,629
• Publication Number:
  US 20110285131A1
• Time in Patent Office: 629 Days
• Field of Search: 310/329, 310/339, 310/319
• US Class Current: 310/339
• CPC Class Codes: F03G 7/08 recovering energy derived from swinging, rolling, pitching or like movements, e.g. from the vibrations of a machine
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02N 2/181 Circuits; Control arrangements or methods
• CPC Class Codes: H02N 2/186 Vibration harvesters

Abstract

A circuit for harvesting electrical energy from a piezoelectric source and for storing the electrical energy in a battery includes an inductor that is configured to store electrical energy. A diode bridge-free switching network is configured to: direct electrical energy from the piezoelectric source to the inductor during a first portion of a piezoelectric charge generating cycle; and direct electrical energy from the inductor to the battery during a second portion of the piezoelectric charge generating cycle.

Claims

1. A circuit for harvesting electrical energy from a piezoelectric source and for storing the electrical energy in a battery, comprising:

(a) an inductor configured to store electrical energy; and

(b) a diode bridge-free switching network that is configured to;

(i) direct electrical energy from the piezoelectric source to the inductor during a first portion of a piezoelectric charge generating cycle; and

(ii) direct electrical energy from the inductor to the battery during a second portion of the piezoelectric charge generating cycle.

2. The circuit of claim 1, wherein the piezoelectric source is coupled between a first node and a second node, the inductor is coupled between a third node and a fourth node, and the battery is coupled between a fifth node and the second node, and wherein the switching network comprises:

(a) a first switch coupled between the first node and the third node;

(b) a second switch coupled between the fourth node and the second node;

(c) a first unidirectional current directing device coupled between the third node and the fifth node and configured to allow current to flow only from the third node to the fifth node;

(d) a second unidirectional current directing device coupled between the fourth node and the fifth node and configured to allow current to flow only from the fourth node to the fifth node; and

(e) a switch state controller that is configured to control the first switch and the second switch.

3. The circuit of claim 2, wherein the switch state controller is configured to:

(a) close both the first switch and the second switch during a first portion of a positive current generating portion of the piezoelectric charge generating cycle;

(b) maintain the first switch in a closed state and open the second switch during a second portion of the positive current generating portion of the piezoelectric charge generating cycle;

(c) close both the first switch and the second switch during a first portion of a negative current generating portion of the piezoelectric charge generating cycle; and

(d) open the first switch and maintain the second switch in a closed state during a second portion of the negative current generating portion of the piezoelectric charge generating cycle.

4. The circuit of claim 2, wherein the switch state controller comprises:

(a) a resistor and a capacitor coupled across the piezoelectric source;

(b) a comparator having a first input coupled to a first terminal of the resistor and a second input coupled to a second terminal of the resistor, the comparator configured to generate an output representative of a voltage event generated by the piezoelectric source;

(c) a delay circuit responsive to the comparator output and configured to generate a delay output that is representative of the comparator output that has been delayed by a predetermined amount of time; and

(d) a logic circuit that is responsive both the comparator output and the delay output and to generate a first switch control signal and a second switch control signal based on a current state of the comparator output and the delay output.

5. The circuit of claim 4, wherein the logic circuit includes an AND gate that is configured to AND the comparator output and the delay output, thereby generating a first switch control signal and wherein the logic circuit includes an NOR gate that is configured to NOR the comparator output and the delay output, thereby generating a second switch control signal.

6. The circuit of claim 5, further comprising:

(a) a first driver element disposed between the AND gate and the first switch; and

(b) a second driver element disposed between the NOR gate and the second switch.

7. The circuit of claim 2, wherein the first switch and the second switch each include a first transistor in series with a second transistor, wherein the first transistor has a leakage current that flows in a first direction and the second transistor has a leakage current that flows in a second direction opposite of the first direction, wherein the first transistor and the second transistor each have a gate that is responsive to a switch control signal from the switch state controller.

8. The circuit of claim 2, wherein each of the first unidirectional current directing device and the second unidirectional current directing device comprises:

(a) a transistor having a gate, a source coupled to a selected one of the third node and the fourth node, and a drain coupled the fifth node; and

(b) a comparator having a negative input coupled to a selected one of the third node and the fourth node, and a positive input coupled to the fifth node and an output coupled the gate of the transistor.

9. The circuit of claim 8, further comprising a driver element disposed between the output of the comparator and the gate of the transistor.

10. A circuit for harvesting electrical energy, comprising:

(a) an alternating current source coupled between a first note and a second node;

(b) a load coupled between a fifth node and the second node;

(c) an inductor, coupled between a third node and a fourth node, configured to store electrical energy;

(d) a first switch coupled between the first node and the third node;

(e) a second switch coupled between the fourth node and the second node;

(f) a first unidirectional current directing device coupled between the third node and the fifth node and configured to allow current to flow only from the third node to the fifth node;

(g) a second unidirectional current directing device coupled between the fourth node and the fifth node and configured to allow current to flow only from the fourth node to the fifth node; and

(h) a switch state controller that is configured to control the first switch and the second switch so as to;

(i) direct electrical energy from the alternating current source to the inductor during a first portion of an alternating current charge generating cycle; and

(ii) direct electrical energy from the inductor to the load during a second portion of the alternating current charge generating cycle.

11. The circuit of claim 10, wherein the alternating current source comprises a piezoelectric element.

12. The circuit of claim 10, wherein the load comprises a battery.

13. The circuit of claim 10, wherein the switch state controller is configured to:

(a) close both the first switch and the second switch during a first portion of a positive current generating portion of the alternating current charge generating cycle;

(b) maintain the first switch in a closed state and open the second switch during a second portion of the positive current generating portion of the alternating current charge generating cycle;

(c) close both the first switch and the second switch during a first portion of a negative current generating portion of the alternating current charge generating cycle; and

(d) open the first switch and maintain the second switch in a closed state during a second portion of the negative current generating portion of the alternating current charge generating cycle.

14. The circuit of claim 10, wherein the switch state controller comprises:

(a) a resistor and a capacitor coupled across the alternating current source;

(b) a comparator having a first input coupled to a first terminal of the resistor and a second input coupled to a second terminal of the resistor, the comparator configured to generate an output representative of a voltage event generated by the alternating current source;

(c) a delay circuit responsive to the comparator output and configured to generate a delay output that is representative of the comparator output that has been delayed by a predetermined amount of time; and

(d) a logic circuit that is responsive both the comparator output and the delay output and to generate a first switch control signal and a second switch control signal based on a current state of the comparator output and the delay output.

15. The circuit of claim 14, wherein the logic circuit includes an AND gate that is configured to AND the comparator output and the delay output, thereby generating a first switch control signal and wherein the logic circuit includes an NOR gate that is configured to NOR the comparator output and the delay output, thereby generating a second switch control signal.

16. The circuit of claim 15, further comprising:

(a) a first driver element disposed between the AND gate and the first switch; and

(b) a second driver element disposed between the NOR gate and the second switch.

17. The circuit of claim 10, wherein the first switch and the second switch each include a first transistor in series with a second transistor, wherein the first transistor has a leakage current that flows in a first direction and the second transistor has a leakage current that flows in a second direction opposite of the first direction, wherein the first transistor and the second transistor each have a gate that is responsive to a switch control signal from the switch state controller.

18. The circuit of claim 10, wherein each of the first unidirectional current directing device and the second unidirectional current directing device comprises:

(a) a transistor having a gate, a source coupled to a selected one of the third node and the fourth node, and a drain coupled the fifth node; and

(b) a comparator having a negative input coupled to a selected one of the third node and the fourth node and a positive input coupled to the fifth node and an output coupled the gate of the transistor.

19. The circuit of claim 18, further comprising a driver element disposed between the output of the comparator and the gate of the transistor.

20. A method of harvesting energy from a piezoelectric current generating source, comprising the steps of:

(a) charging, from the piezoelectric current generating source, an inductor with a first bias during a first positive portion of a piezoelectric charge generating cycle;

(b) directing current from the inductor to a positive terminal of a load during a second positive portion of the piezoelectric charge generating cycle by coupling a first terminal of the inductor to the positive terminal of the load along a first circuit path;

(c) charging, from the piezoelectric current generating source, the inductor with a second bias, opposite the first bias, during a first negative portion of the piezoelectric charge generating cycle; and

(d) directing current from the inductor to the positive terminal of the load during a second negative portion of the piezoelectric charge generating cycle by coupling a second terminal of the inductor, different from the first terminal of the inductor, to the positive terminal of the load along a second circuit path, different from the first circuit path.