Delay lines, methods for delaying a signal, and delay lock loops
First Claim
1. A delay circuit, comprising:
- a delay line comprising a plurality of inverting delay devices coupled to each other in series from a first inverting delay device to a last inverting delay device, the first inverting delay device having an input receiving a reference clock signal; and
an exit tree coupled to the delay line, the exit tree comprising;
a plurality of first logic devices each of which has a first input coupled to a respective one of the inverting delay devices and a second input coupled to receive a respective enable signal; and
a pair of second logic devices each of which has a plurality of input terminals coupled to respective outputs of a plurality of the first logic devices that are coupled to alternating ones of the inverting delay devices, one of the second logic devices being coupled to the outputs of the first logic devices that are different from the outputs of the first logic devices to which the other of the first logic devices are coupled.
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Accused Products
Abstract
Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.
42 Citations
20 Claims
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1. A delay circuit, comprising:
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a delay line comprising a plurality of inverting delay devices coupled to each other in series from a first inverting delay device to a last inverting delay device, the first inverting delay device having an input receiving a reference clock signal; and an exit tree coupled to the delay line, the exit tree comprising; a plurality of first logic devices each of which has a first input coupled to a respective one of the inverting delay devices and a second input coupled to receive a respective enable signal; and a pair of second logic devices each of which has a plurality of input terminals coupled to respective outputs of a plurality of the first logic devices that are coupled to alternating ones of the inverting delay devices, one of the second logic devices being coupled to the outputs of the first logic devices that are different from the outputs of the first logic devices to which the other of the first logic devices are coupled. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A delay circuit, comprising:
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a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device; and a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. - View Dependent Claims (9, 10, 11, 12)
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13. A delay circuit, comprising:
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a delay line configured to receive an input clock signal and provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device; and a two-phase exit tree a coupled to the delay line and configured to provide first and second output clock signals responsive to the delayed clock signals. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification