Silicon-on-insulator high power amplifiers

• US 8,368,469 B2
• Filed: 03/10/2011
• Issued: 02/05/2013
• Est. Priority Date: 03/10/2010
• Status: Active Grant

• Current Assignee: Purdue Research Foundation (Purdue University)
• Original Assignee: Purdue Research Foundation (Purdue University)
• Inventors: Mohammadi, Saeed, Helmi, Sultan R., Chen, Jing-Hwa, Robison, Andrew J.
• Primary Examiner(s): Choe, Henry
• Application Number:
  US13/044,989
• Publication Number:
  US 20110227648A1
• Time in Patent Office: 698 Days
• Field of Search: 330/277, 330/307, 330/295, 330/124.R, 330/311
• US Class Current: 330/277
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H03F 1/0272 by using a signal derived from the output signal
• CPC Class Codes: H03F 2200/537 A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2203/45394 the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
• CPC Class Codes: H03F 2203/45731 the LC comprising a transformer
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/426 with junction-FET's
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence

Abstract

Illustrative embodiments of a power amplifier are disclosed which include a plurality of amplifier cells, each having an input and an output. The plurality of amplifier cells are formed on a semiconductor substrate such that the outputs of the plurality of amplifier cells are electrically coupled in series. Each of the plurality of amplifier cells may comprise a first transistor that is electrically insulated from the semiconductor substrate and a first feedback resistor configured to dynamically bias the first transistor.

Claims

1. A power amplifier comprising:

a plurality of amplifier cells each having an input and an output, the plurality of amplifier cells being formed on a semiconductor substrate such that the outputs of the plurality of amplifier cells are electrically coupled in series, wherein each of the plurality of amplifier cells comprises;

a first transistor that is electrically insulated from the semiconductor substrate;

a first feedback resistor configured to dynamically bias the first transistor; and

a second transistor that is electrically insulated from the semiconductor substrate, the first and second transistors of each of the plurality of amplifier cells being configured as a cascode amplifier; and

wherein the first transistor of each of the plurality of amplifier cells is arranged in a common-source configuration and the second transistor of each of the plurality of amplifier cells is arranged in a common-gate configuration.

2. The power amplifier of claim 1, wherein the first transistor is electrically insulated from the semiconductor substrate by at least one of a buried oxide layer, an oxide trench, and an etched trench.

3. The power amplifier of claim 1, wherein the plurality of amplifier cells comprises at least five amplifier cells.

4. The power amplifier of claim 1, further comprising a plurality of transformers, each of the plurality of transformers being configured to couple an input signal to the input of one of the plurality of amplifier cells.

5. The power amplifier of claim 4, wherein the plurality of transformers are electrically coupled in series.

6. The power amplifier of claim 1, wherein each of the plurality of amplifier cells further comprises a second feedback resistor configured to dynamically bias the second transistor.

7. The power amplifier of claim 1, wherein each of the plurality of amplifier cells further comprises a biasing network that includes the first feedback resistor and that is configured to dynamically bias the first and second transistors.

8. The power amplifier of claim 7, wherein each of the plurality of amplifier cells further comprises a diode-connected transistor configured to provide a direct current bias to the first transistor.

9. The power amplifier of claim 1, wherein each of the plurality of amplifier cells further comprises an inductor electrically coupled to the first transistor, the inductor being configured to tune out a parasitic capacitance between the first transistor and the semiconductor substrate.

10. The power amplifier of claim 1, wherein the first and second transistors of each of the plurality of amplifier cells comprise silicon-on-insulator transistors.

11. The power amplifier of claim 1, wherein the first feedback resistor of each of the plurality of amplifier cells is electrically coupled between a drain terminal and a gate terminal of the first transistor.

12. The power amplifier of claim 6, wherein:

the first feedback resistor of each of the plurality of amplifier cells is electrically coupled between a drain terminal and a gate terminal of the first transistor; and

the second feedback resistor of each of the plurality of amplifier cells is electrically coupled between a drain terminal and a gate terminal of the second transistor.

13. The power amplifier of claim 7, wherein:

the biasing network of each of the plurality of amplifier cells further includes a second feedback resistor that is electrically coupled between a drain terminal and a gate terminal of the second transistor; and

the first feedback resistor of the biasing network of each of the plurality of amplifier cells is electrically coupled between a gate terminal of the first transistor and the gate terminal of the second transistor.

14. The power amplifier of claim 13, wherein the biasing network of each of the plurality of amplifier cells further includes a diode-connected transistor configured to provide a direct current bias to the first transistor.

15. The power amplifier of claim 9, wherein each of the plurality of amplifier cells further comprises a capacitor electrically coupled in series with the inductor between the first transistor and a ground node.

16. The power amplifier of claim 1, wherein the outputs of the plurality of amplifier cells that are electrically coupled in series provide an overall output impedance of about 50 ohms.