Nonvolatile semiconductor memory device

• US 8,369,142 B2
• Filed: 03/16/2010
• Issued: 02/05/2013
• Est. Priority Date: 04/14/2009
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Futatsuyama, Takuya
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US12/724,636
• Publication Number:
  US 20100259980A1
• Time in Patent Office: 1,057 Days
• Field of Search: 365/185.03, 365/185.14, 365/189.16, 365/189.15, 365/230.06
• US Class Current: 365/185.03
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/045 Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Abstract

A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a cell unit including a first and a second selection gate transistor and a memory string provided between said first and second selection gate transistors and including a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and

a data write circuit operative to write data into said memory cell,

wherein the number of program stages for at least one of memory cells on both ends of said memory string is lower than the number of program stages for other memory cells,

said data write circuit executes the first stage program to said memory cell having the number of program stages lower than the number of program stages for said other memory cells after the first stage program to said other memory cells,

the number of program stages for a first memory cell counted from said first selection gate transistor is N (N=an integer of 1 or more), and the number of program stages for other memory cells is M (M=an integer layer than N),

said data write circuit executes the i₁-th stage (i₁=an integer of 1-N) program to said first memory cell after execution of the i₁-th stage program to a second memory cell counted from said first selection gate transistor, and

said data write circuit executes the i₂-th stage (i₂=an integer of 1-M) program to the k-th (k=an integer of 3 or more) memory cell counted from said first selection gate transistor after execution of the i₂-th stage program to the (k−

1)-the memory cell.

2. The nonvolatile semiconductor memory device according to claim 1, wherein the number of program stages for at least one of memory cells on both ends of said memory string and the number of program stages for other memory cells have a difference by 2 or more.

3. The nonvolatile semiconductor memory device according to claim 1, wherein said memory cells on both ends of said memory string store 1 bit, and other memory cells store 3 bits.

4. The nonvolatile semiconductor memory device according to claim 1, wherein said cell unit includes a dummy cell having a structure equal to a memory cell between said first selection gate transistor and said memory string and/or between said second selection gate transistor and said memory string.

5. The nonvolatile semiconductor memory device according to claim 1, wherein the number of program stages for the first memory cell counted from said first selection gate transistor is 1, and the number of program stages for other memory cells is 3,

said data write circuit executes the first stage program to said first memory cell after execution of the second stage program to the second memory cell counted from said first selection gate transistor,

said data write circuit executes the i-th stage (i=an integer of 1-3) program to the k-th (k=an integer of 3 or more) memory cell counted from said first selection gate transistor after execution of the i-th stage program to the (k−

1)-th memory cell.

6. The nonvolatile semiconductor memory device according to claim 1, wherein the number of program stages for the first memory cell counted from said first selection gate transistor is 1, and the number of program stages for other memory cells is 3,

said data write circuit executes the first stage program to said first memory cell after execution of the first stage program to the second memory cell counted from said first selection gate transistor,

said data write circuit executes the i-th stage (i=an integer of 1-3) program to the k-th (k=an integer of 3 or more) memory cell counted from said first selection gate transistor after execution of the i-th stage program to the (k−

1)-th memory cell.

7. The nonvolatile semiconductor memory device according to claim 1, wherein the number of program stages for the first memory cell counted from said second selection gate transistor is 1, and the number of program stages for other memory cells is 3,

said data write circuit executes the first stage program to said first memory cell after execution of the first stage program to the second memory cell counted from said second selection gate transistor,

said data write circuit executes the i-th stage (i=an integer of 1-3) program to the k-th (k=an integer of 2 or more) memory cell counted from said second selection gate transistor after execution of the i-th stage program to the (k+1)-th memory cell.

8. The nonvolatile semiconductor memory device according to claim 1, wherein the number of program stages for the first memory cell counted from said second selection gate transistor is 1, and the number of program stages for other memory cells is 3,

said data write circuit executes the first stage program to said first memory cell after execution of the second stage program to the second memory cell counted from said second selection gate transistor,

said data write circuit executes the i-th stage (i=an integer of 1-3) program to the k-th (k=an integer of 2 or more) memory cell counted from said second selection gate transistor after execution of the i-th stage program to the (k+1)-th memory cell.

9. The nonvolatile semiconductor memory device according to claim 1, wherein said memory string includes N memory cells (N=an integer of 4 or more), and the numbers of program stages for the first memory cell and for the N-th memory cell of these memory cells counted from said first selection gate transistor are 2, and the number of program stages for other memory cells is 3,

said data write circuit executes the i₁-th stage (i₁=1 or 2) program to said first memory cell after execution of the i₁-th stage program to the second memory cell counted from said first selection gate transistor,

said data write circuit executes the i₂-th stage (i₂=1 or 2) program to said N-th memory cell after execution of the i₂-th stage program to the (N-1)-th memory cell counted from said first selection gate transistor,

said data write circuit executes the i₃-th stage (i₃=an integer of 1-3) program to the k-th (k=3 to N−

1) memory cell counted from said first selection gate transistor after execution of the i₃-th stage program to the (k−

1)-th memory cell.

10. The nonvolatile semiconductor memory device according to claim 1, wherein the number of program stages for the first memory cell counted from said first selection gate transistor is 1, and the number of program stages for other memory cells is 2,

said data write circuit executes the first stage program to said first memory cell after execution of the first stage program to the second memory cell counted from said first selection gate transistor,

said data write circuit executes the i-th stage (i=an integer of 1-3) program to the k-th (k=an integer of 3 or more) memory cell counted from said first selection gate transistor after execution of the i-th stage program to the (k−

1)-th memory cell.

11. A nonvolatile semiconductor memory device, comprising:

a cell unit including a first and a second selection gate transistor and a memory string provided between said first and second selection gate transistors and including a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and

a data write circuit operative to write data into said memory cell,

wherein the number of program stages for at least one of memory cells on both ends of said memory string is lower than the number of program stages for other memory cells,

said data write circuit, on writing data into said memory string, after execution of the first program and before execution of the last program to a certain memory cell adjacent to said memory cell having the lower number of program stages, executes the first program through the last program to said memory cell having the lower number of program stages, adjacent to said certain memory cell,

the number of program stages for a first memory cell counted from said first selection gate transistor is N (N=an integer of 1 or more), and the number of program stages for other memory cells is M (M=an integer layer than N),

said data write circuit executes the i₁-th stage (i₁=an integer of 1-N) program to said first memory cell after execution of the i₁-th stage program and before execution of the M-th stage program to a second memory cell counted from said first selection gate transistor, and

said data write circuit executes the i₂-th sage (i₂=an integer of 1-M) program to the k-th (k=an integer of 3 or more) memory cell counted from said first selection gate transistor after execution of the i₂-th stage program to the (k−

1)-the memory cell.

12. The nonvolatile semiconductor memory device according to claim 11, wherein the number of program stages for at least one of memory cells on both ends of said memory string and the number of program stages for other memory cells have a difference by 2 or more.

13. The nonvolatile semiconductor memory device according to claim 11, wherein said memory cells on both ends of said memory string store 1 bit, and other memory cells store 3 bits.

14. The nonvolatile semiconductor memory device according to claim 11, wherein said cell unit includes a dummy cell having a structure equal to a memory cell between said first selection gate transistor and said memory string and/or between said second selection gate transistor and said memory string.