Memory word line boost using thin dielectric capacitor
First Claim
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1. A memory, comprising:
- a word line; and
a word line boost circuit including;
a first capacitor having a first capacitor dielectric thickness; and
a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness,wherein the word line boost circuit is configured to supply a first high voltage that is higher than a power supply voltage to the word line during a first operation of the memory by utilizing the first capacitor.
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Abstract
A memory includes a word line and a word line boost circuit. The word line boost circuit includes a capacitor having a capacitor dielectric thickness, and a transmission gate coupled to the word line and the capacitor. The transmission gate has a gate-dielectric thickness that is greater than the capacitor dielectric thickness. The word line boost circuit is configured to supply a high voltage that is higher than a power supply voltage to the word line during an operation of the memory by utilizing the capacitor.
6 Citations
20 Claims
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1. A memory, comprising:
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a word line; and a word line boost circuit including; a first capacitor having a first capacitor dielectric thickness; and a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness, wherein the word line boost circuit is configured to supply a first high voltage that is higher than a power supply voltage to the word line during a first operation of the memory by utilizing the first capacitor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for boosting a word line of a memory, comprising:
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supplying a power supply voltage to a word line of the memory; charging a first capacitor having a first capacitor dielectric thickness in a word line boost circuit to the power supply voltage; and during a first operation of the memory, boosting a first voltage level of the word line to a first high voltage that is higher than the power supply voltage through a transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A memory, comprising:
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a word line; and a word line boost circuit including; a first capacitor having a first capacitor dielectric thickness; a pulse generator that supplies a pulse; a delay buffer coupled to the pulse generator and the first capacitor; a second capacitor coupled to the pulse generator, the second capacitor having a second capacitor dielectric thickness that is greater than the first capacitor dielectric thickness; a switch coupled to the second capacitor and the word line; and a transmission gate coupled to the word line and the first capacitor, the transmission gate having a gate-dielectric thickness that is greater than the first capacitor dielectric thickness; wherein the second capacitor is coupled to a bulk of a PMOS transistor of the transmission gate, the switch is configured to be closed during a first operation of the memory, and the word line boost circuit is configured to supply a first high voltage that is higher than a power supply voltage to the word line during the first operation of the memory by utilizing the first capacitor. - View Dependent Claims (20)
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Specification