System and apparatus with a memory controller configured to control access to randomly accessible non-volatile memory
First Claim
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1. A system comprising:
- a printed circuit board includinga first memory channel having a plurality of DRAM memory modules plugged into a first plurality of sockets;
a first memory controller coupled to the first plurality of sockets in the first memory channel by a first memory channel bus with a first plurality of traces, the first memory controller to control access to the plurality of DRAM memory modules;
a second memory channel having a first plurality of non-volatile memory modules plugged into a second plurality of sockets, the first plurality of non-volatile memory modules to conserve power; and
a second memory controller coupled to the second plurality of sockets in the second memory channel by a second memory channel bus with a second plurality of traces differing from the first plurality of traces, the second memory controller to control access to the first plurality of non-volatile memory modules.
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Abstract
An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.
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Citations
7 Claims
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1. A system comprising:
a printed circuit board including a first memory channel having a plurality of DRAM memory modules plugged into a first plurality of sockets; a first memory controller coupled to the first plurality of sockets in the first memory channel by a first memory channel bus with a first plurality of traces, the first memory controller to control access to the plurality of DRAM memory modules; a second memory channel having a first plurality of non-volatile memory modules plugged into a second plurality of sockets, the first plurality of non-volatile memory modules to conserve power; and a second memory controller coupled to the second plurality of sockets in the second memory channel by a second memory channel bus with a second plurality of traces differing from the first plurality of traces, the second memory controller to control access to the first plurality of non-volatile memory modules. - View Dependent Claims (2, 3, 4, 5, 6, 7)
Specification