System and apparatus with a memory controller configured to control access to randomly accessible non-volatile memory

• US 8,370,547 B2
• Filed: 07/06/2010
• Issued: 02/05/2013
• Est. Priority Date: 09/28/2006
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Virident Systems Inc. (Western Digital Corporation)
• Inventors: Karamcheti, Vijay, Ganapathy, Kumar, Okin, Kenneth Alan, Parekh, Rajesh
• Primary Examiner(s): Lee, Chun-Kuan
• Assistant Examiner(s): MARTINEZ, DAVID E
• Application Number:
  US12/831,233
• Publication Number:
  US 20100274957A1
• Time in Patent Office: 945 Days
• Field of Search: 710/62, 710/74
• US Class Current: 710/62
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 13/12 using hardware independent of the central processor, e.g. channel or peripheral processor
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/25 Using a specific main memory architecture
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus includes a printed circuit board with a plurality of printed circuit board traces, a memory controller mounted on the printed circuit board coupled to one or more of the plurality of printed circuit board traces, a plurality of non-volatile type of memory integrated circuits coupled to the printed circuit board, and a plurality of support integrated circuits coupled between the memory controller and the plurality of non-volatile type of memory integrated circuits.

Claims

1. A system comprising:

a printed circuit board including

a first memory channel having a plurality of DRAM memory modules plugged into a first plurality of sockets;

a first memory controller coupled to the first plurality of sockets in the first memory channel by a first memory channel bus with a first plurality of traces, the first memory controller to control access to the plurality of DRAM memory modules;

a second memory channel having a first plurality of non-volatile memory modules plugged into a second plurality of sockets, the first plurality of non-volatile memory modules to conserve power; and

a second memory controller coupled to the second plurality of sockets in the second memory channel by a second memory channel bus with a second plurality of traces differing from the first plurality of traces, the second memory controller to control access to the first plurality of non-volatile memory modules.

2. The system of claim 1, further comprising:

a third memory channel having a second plurality of non-volatile memory modules plugged into a third plurality of sockets, the second plurality of non-volatile memory modules differing from the first plurality of non-volatile memory modules, the second plurality of non-volatile memory modules to conserve power and expand memory capacity of main memory; and

a third memory controller coupled to the third plurality of sockets in the third memory channel by a third memory channel bus with a third plurality of traces differing from the first and second pluralities of traces, the third memory controller to control access to the second plurality of non-volatile memory modules.

3. The system of claim 1, further comprising:

a processor coupled to the first memory controller and the second memory controller.

4. The system of claim 1, wherein

the second memory controller is a secondary memory controller;

and the system further includes

a third memory controller coupled between the processor and the second memory controller.

5. The system of claim 1, wherein

the first memory controller and the second memory controller are integrated with

a processor into a single package coupled to the first memory channel and the second memory channel.

6. The system of claim 1, wherein

a first data communication protocol supports a write access to the plurality of DRAM memory modules in the first memory channel different from a write access supported by a second data communication protocol to the first plurality of non-volatile memory modules in the second memory channel.

7. The system of claim 2, wherein

a first data communication protocol supports a write access to the plurality of DRAM memory modules in the first memory channel different from a write access supported by a second data communication protocol to the first plurality of non-volatile memory modules in the second memory channel, and

a third data communication protocol to access the second plurality of non-volatile memory modules in the third memory channel differs from the second data communication protocol to access the first plurality of non-volatile memory modules in the second memory channel.