System and method for increasing capacity, performance, and flexibility of flash storage

• US 8,370,566 B2
• Filed: 10/18/2011
• Issued: 02/05/2013
• Est. Priority Date: 10/05/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Danilak, Radoslav, Smith, Michael J. S., Rajan, Suresh
• Primary Examiner(s): PEUGH, BRIAN R
• Application Number:
  US13/276,212
• Publication Number:
  US 20120124277A1
• Time in Patent Office: 476 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

In one embodiment, an interface circuit is configured to couple to one or more flash memory devices and is further configured to couple to a host system. The interface circuit is configured to present at least one virtual flash memory device to the host system, wherein the interface circuit is configured to implement the virtual flash memory device using the one or more flash memory devices to which the interface circuit is coupled.

Claims

1. An interface circuit configured to couple to one or more flash memory devices, each having a respective capacity, and further configured to couple to a host system, the interface circuit comprising:

a read-only memory (ROM) storing fixed configuration information associated with the one or more flash memory devices; and

discovery logic configured to;

detect a physical configuration of the one or more flash memory devices, and determine a virtual configuration for the one or more flash memory devices based on, at least in part, the detected physical configuration and based on, at least in part, the fixed configuration information stored in the ROM; and

configuration logic configured to;

store the virtual configuration as a virtual flash memory device having a capacity.

2. The interface circuit as recited in claim 1 wherein the virtual flash memory device has a capacity greater than the capacity of any one of the one or more flash memory devices.

3. The interface circuit as recited in claim 1 wherein the virtual flash memory device has a capacity equal to a sum of the capacities of the one or more flash memory devices.

4. The interface circuit as recited in claim 1 wherein the interface circuit is configured to compute a parameter of the virtual flash memory device.

5. The interface circuit as recited in claim 4 wherein the parameter is reported to the host system.

6. The interface circuit as recited in claim 1 wherein the interface circuit is configured to translate a protocol implemented by the host system to a protocol implemented by the one or more flash memory devices.

7. The interface circuit as recited in claim 1 wherein the interface circuit is configured to detect a block of bad data locations in the virtual flash memory device and to remap addresses in the block from a one set of storage locations in the one or more flash memory devices to a different set of storage locations in the one or more flash memory devices.

8. The interface circuit as recited in claim 1 wherein the interface circuit is configured to generate an erasure operation independent of a write operation.

9. The interface circuit as recited in claim 8 wherein the erasure operation erases a block in the one of the one or more flash memory devices, wherein the block has been marked as garbage for garbage collection.

10. The interface circuit as recited in claim 8 wherein the erasure operation is generated by the interface circuit to pre-erase unused blocks in the one or more flash memory devices.

11. The interface circuit as recited in claim 1 further comprising one or more buffers configured to store write operations provided by the host system, wherein the interface circuit is configured to report that an erasure operation corresponding to a write operation has completed prior to actual completion of the erasure operation, and wherein the interface circuit is configured to store the write operation in the buffer until the erasure operation is actually complete.

12. The interface circuit as recited in claim 1 further comprising a translation unit configured to receive a request from the host system to access at least one of the one or more flash memory devices, wherein information associated with the request is based on the virtual configuration for the one or more virtual flash memory devices, and translate the request received from the host system to a translated request that includes information associated with the physical configuration for the one or more flash memory devices.

13. The interface circuit as recited in claim 1 wherein the configuration logic is further configured to present a first standard interface to the host system and to provide a second interface to the one or more flash memory devices that differ from the first standard interface.

14. An apparatus comprising:

one or more flash memory devices; and

an interface circuit coupled to the one or more flash memory devices and further configured to couple to a host system, wherein the interface circuit comprises;

a read-only memory (ROM) storing fixed configuration information associated with the one or more flash memory devices; and

discovery logic configured to;

detect a physical configuration for the one or more flash memory devices, and determine a virtual configuration for the one or more flash memory devices based on, at least in part, the detected physical configuration and based on, at least in part, the fixed configuration information stored in the ROM; and

configuration logic configured to;

store the virtual configuration as a virtual flash memory device.

15. The apparatus as recited in claim 14 wherein the interface circuit and the one or more flash memory devices are stacked.

16. The apparatus as recited in claim 14 wherein the one or more flash memory devices and the interface circuit are integrated onto a single semiconductor substrate.

17. The apparatus as recited in claim 14 wherein the interface circuit further comprises a translation unit configured to receive a request from the host system to access at least one of the one or more flash memory devices, wherein information associated with the request is based on the virtual configuration for the one or more virtual flash memory devices, and translate the request received from the host system to a translated request that includes information associated with the physical configuration for the one or more flash memory devices.

18. The apparatus as recited in claim 14 wherein the configuration logic is further configured to present a first standard interface to the host system and to provide a second interface to the one or more flash memory devices that differ from the first standard interface.

19. The apparatus as recited in claim 18 wherein the first standard interface is pin-compatible with a previous generation of flash memory devices.