Adaptive control of operating and body bias voltages

• US 8,370,658 B2
• Filed: 07/14/2009
• Issued: 02/05/2013
• Est. Priority Date: 06/22/2004
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Sheng, Eric Chen-Li, Ward, Matthew Robert
• Primary Examiner(s): Suryawanshi, Suresh
• Application Number:
  US12/502,902
• Publication Number:
  US 20100257389A1
• Time in Patent Office: 1,302 Days
• Field of Search: 713/300
• US Class Current: 713/320
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Adaptive control of operating and body bias voltages. In accordance with a first embodiment of the present invention, a desirable operating frequency for the microprocessor is determined. Information stored within and specific to the microprocessor is accessed. The information can comprise coefficients of a quadratic approximation of a frequency-voltage characteristic of the microprocessor for a set of body biasing conditions. An efficient voltage for operating the microprocessor at the desirable operating frequency is computed. The microprocessor is operated at the efficient voltage and the set of body biasing conditions.

Claims

1. A method of manufacturing a microprocessor comprising:

accessing an unpackaged microprocessor;

determining a set of body biasing voltages to be used by said microprocessor to operate in a low power mode; and

encoding information of said set of body biasing voltages into said microprocessor.

2. The method as described in claim 1 further comprising encoding information of a frequency-voltage characteristic of said microprocessor at said set of body biasing voltages into said microprocessor.

3. The method as described in claim 1 further comprising determining a second set of body biasing voltages required by said microprocessor to operate at a maximum frequency.

4. The method as described in claim 3 further comprising encoding information of said second set of body biasing voltages into said microprocessor.

5. The method as described in claim 4 further comprising encoding information of a second frequency-voltage characteristic of said microprocessor at said second set of body biasing voltages into said microprocessor.

6. The method as described in claim 5 wherein said determining is performed prior to packaging said microprocessor.

7. The method as described in claim 6 wherein said determining is performed at a wafer level.

8. The method as described in claim 7 wherein said encoding is also performed at said wafer level.

9. A method of manufacturing a microprocessor comprising:

accessing an unpackaged microprocessor;

determining a set of body biasing voltages to be used by said microprocessor to operate at a maximum frequency; and

encoding information of said set of body biasing voltages into said microprocessor.

10. The method as described in claim 9 wherein said determining is performed prior to packaging said microprocessor.

11. The method as described in claim 9 wherein said determining is performed at a wafer level.

12. The method as described in claim 11 wherein said encoding is also performed at said wafer level.