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Power management with dynamic frequency adjustments

  • US 8,370,663 B2
  • Filed: 02/11/2008
  • Issued: 02/05/2013
  • Est. Priority Date: 02/11/2008
  • Status: Active Grant
First Claim
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1. A system for adjusting clock frequency, said system comprising:

  • a device operable for executing a task; and

    a processor coupled to said device, wherein said processor specifies a value for a frequency for a clock signal used by said device and thereafter said processor is placed in a reduced power mode;

    wherein said device is operable to perform said task after said processor is placed in said reduced power mode until a triggering event causes said device to send an interrupt to said processor;

    wherein in response to said interrupt said processor awakens to dynamically adjust said frequency of said clock signal so that a metric satisfies a first condition, and wherein if said frequency of said clock signal returns to said value then said processor is again placed in said reduced power mode.

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