Power management with dynamic frequency adjustments

• US 8,370,663 B2
• Filed: 02/11/2008
• Issued: 02/05/2013
• Est. Priority Date: 02/11/2008
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Frid, Aleksandr, Sriram, Parthasarathy
• Primary Examiner(s): DU, THUAN N
• Application Number:
  US12/029,375
• Publication Number:
  US 20090204830A1
• Time in Patent Office: 1,821 Days
• Field of Search: 713/310, 713/322, 713/323
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A central processing unit (CPU) can specify an initial (e.g., baseline) frequency for a clock signal used by a device to perform a task. The CPU is then placed in a reduced power mode. The device performs the task after the CPU is placed in the reduced power mode until a triggering event causes the device to send an interrupt to the CPU. In response to the interrupt, the CPU awakens to dynamically adjust the clock frequency. If the clock frequency is reset to the baseline value, then the CPU is again placed in the reduced power mode.

Claims

1. A system for adjusting clock frequency, said system comprising:

a device operable for executing a task; and

a processor coupled to said device, wherein said processor specifies a value for a frequency for a clock signal used by said device and thereafter said processor is placed in a reduced power mode;

wherein said device is operable to perform said task after said processor is placed in said reduced power mode until a triggering event causes said device to send an interrupt to said processor;

wherein in response to said interrupt said processor awakens to dynamically adjust said frequency of said clock signal so that a metric satisfies a first condition, and wherein if said frequency of said clock signal returns to said value then said processor is again placed in said reduced power mode.

2. The system of claim 1 wherein said interrupt is sent based on a measure of buffer capacity of a buffer associated with said device.

3. The system of claim 1 wherein said interrupt is sent if a measure of workload is predicted to change during execution of said task.

4. The system of claim 1 wherein said metric is based on an amount of time said device is idle while said task is executed.

5. The system of claim 4 wherein said processor increases said value of said frequency of said clock signal if said metric is less than a corresponding threshold value and decreases said value for said frequency for said clock signal if said metric is more than a corresponding threshold value.

6. The system of claim 4 wherein said amount of time is measured over a sample interval, wherein said sample interval is extended in length if said value for said frequency of said clock signal is reduced.

7. The system of claim 1 wherein said value for said frequency of said clock signal is specified according to a type of said task.

8. The system of claim 1 wherein reduced power mode comprises power gating said processor.

9. A method of managing power consumption in an electronic system, said method comprising:

with a processor operating in a first power mode, selecting a device to perform a task and selecting a value for a frequency for a clock used by said device;

entering a reduced power mode at said processor after said device and said value are selected, wherein said frequency of said clock remains set to said value until a triggering event causes said device to send an interrupt to said processor;

awakening said processor in response to said interrupt so that said processor can dynamically adjust said value; and

re-entering said reduced power mode at said processor if said frequency of said clock is adjusted to said value.

10. The method of claim 9 further comprising:

monitoring a measure of buffer capacity associated with said device; and

sending said interrupt if said measure is less than a threshold.

11. The method of claim 9 further comprising sending said interrupt if an increase in workload associated with performing said task is predicted.

12. The method of claim 9 further comprising:

with said processor in said first operating mode subsequent to said awakening, monitoring a metric that corresponds to an amount of time said device is idle while performing said task;

increasing said value of said frequency for said clock if said metric is less than a corresponding threshold value; and

decreasing said value of said frequency for said clock if said metric is greater than a corresponding threshold value.

13. The method of claim 9 wherein said selecting further comprises selecting said value for said frequency for said clock depending on a type of said task.

14. The method of claim 9 further comprising power gating said processor in said reduced power mode.

15. A method of managing power consumption in an electronic system, said method comprising:

with a processor in a reduced power mode, operating a device to perform a task using a clock signal having a frequency set to a first frequency value;

sending an interrupt to said processor in response to a triggering event, wherein said triggering event indicates a requirement to increase said frequency of said clock signal, wherein said interrupt causes said processor to exit said reduced power mode;

subsequent to said interrupt, increasing said frequency of said clock signal to a second frequency value specified by said processor;

subsequent to increasing said frequency of said clock signal, monitoring a metric associated with said device; and

comparing said metric to a threshold and adjusting said frequency of said clock signal based on a result of said comparing.

16. The method of claim 15 further comprising:

operating said processor in a first power mode to specify said first frequency value;

operating said processor in said reduced power mode after said first frequency value is specified and until said interrupt; and

returning said processor to said reduced power mode if said frequency of said clock signal is adjusted to said first frequency value.

17. The method of claim 15 further comprising:

monitoring a measure of buffer capacity associated with said device; and

sending said interrupt if said measure is less than a threshold.

18. The method of claim 15 further comprising sending said interrupt in response to predicting an increase in workload associated with performing said task.

19. The method of claim 15 wherein said metric corresponds to an amount of time said device is idle while performing said task.

20. The method of claim 15 wherein said adjusting comprises:

increasing said frequency of said clock signal if said metric is less than a corresponding threshold value; and

decreasing said frequency of said clock signal if said metric is greater than a corresponding threshold value.