Cable interconnection techniques

• US 8,370,704 B2
• Filed: 03/09/2009
• Issued: 02/05/2013
• Est. Priority Date: 03/09/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ganga, Ilango S., Mellitz, Richard I.
• Primary Examiner(s): LOHN, JOSHUA A
• Application Number:
  US12/381,194
• Publication Number:
  US 20100229067A1
• Time in Patent Office: 1,429 Days
• Field of Search: 714/752, 714/757, 714/775
• US Class Current: 714/757
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof
• CPC Class Codes: H04L 1/004 by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00

Abstract

Techniques are described that can extend the transmission rate over cable. Multiple cables can be used to increase the transmission rate. The transmission standard applied for each cable can be an Ethernet backplane standard such as IEEE 802.3ap (2007). Data can be assigned to virtual lanes prior to transmission over a cable. Forward error correction may be applied to each virtual lane prior to transmission over cable. Forward error correction may be negotiated over a single virtual lane and then applied to all virtual lanes.

Claims

1. A computer-implemented method, the method comprising:

identifying a start position of a Forward Error Correction (FEC) block received from a lane as Word 0 of the FEC block based at least on parity bits of the FEC block;

performing data alignment for data transmitted over different lanes, wherein performing data alignment comprises detecting FEC frame markers and wherein each FEC frame marker comprises Word 0 that is also used to identify a start position of the FEC block, and

reporting Global Sync for a link in response to alignment of data on all lanes.

2. The method of claim 1, further comprising:

performing FEC decoding based at least in part on signals received from a lane.

3. The method of claim 1, further comprising:

receiving multiple signals transmitted over the different lanes;

performing FEC decoding based at least in part on a signal received from a lane of the different lanes; and

performing FEC decoding based at least in part on a signal received from another lane of the different lanes.

4. The method of claim 3, further comprising:

indicating FEC error through at least every alternate sync bit.

5. An apparatus comprising:

a data alignment device configured to;

identify a start position of an FEC block received from a lane as Word 0 of the FEC block based at least on parity bits of the FEC block and also to perform data alignment for data transmitted over different lanes, wherein to detect FEC frame markers, the data alignment device is to perform data alignment for data transmitted over different lanes, wherein each FEC frame marker comprises Word 0 that is also used to identify a start position of the FEC block, and the data alignment device is to report Global Sync for a link in response to alignment of data on all lanes.

6. The apparatus of claim 5, further comprising:

an FEC encoder and

an FEC decoder, wherein;

the FEC encoder logic is to encode content using (2112,

     2080) code blocks independently for each of the lanes and

the FEC decoder logic is to decode (2112,

     2080) code blocks independently on each of the lanes and is to provide 64B/66B blocks.

7. The apparatus of claim 6, wherein the FEC decoder logic is to indicate error through sync bits.

8. The apparatus of claim 6, wherein

the FEC decoder logic is to indicate to the PCS sublayer logic errors in at least every alternate 64B/66B block sync bit.

9. The apparatus of claim 6, wherein:

each lane comprises a physical lane and each physical lane carries at least one virtual lane and

the FEC encoder and FEC decoder operate on each virtual lane independently.

10. An apparatus comprising:

a forward error correction (FEC) layer logic, the FEC layer logic comprising FEC encoder logic and FEC decoder logic;

a physical coding sublayer (PCS) sublayer logic;

logic to identify a start position of an FEC block received from a lane as Word 0 of the FEC block based at least on parity bits of the FEC block and also to perform data alignment for data transmitted over different lanes, wherein the logic is to detect FEC frame markers to perform data alignment for data transmitted over the different lanes, wherein each FEC frame marker comprises Word 0 that is also used to identify a start position of the FEC block, and the logic is to cause report of Global Sync for a link in response to alignment of data on all lanes, wherein

the PCS sublayer logic is to provide at least two lanes to the FEC encoder logic;

the PCS sublayer logic is to receive at least two lanes from the FEC decoder logic;

the FEC encoder logic is to encode content using (2112,

     2080) code blocks on each of the lanes, wherein the FEC encoder logic is to encode content independently for each of the lanes,

the FEC decoder logic is to decode (2112,

     2080) code blocks independently on each of the lanes and is to provide 64B/66B blocks,

the FEC decoder logic is to indicate error through sync bits to the PCS sublayer logic,

signals transmitted over the lanes are derived from a same signal source, and

an aggregate transmission rate of the signals transmitted over the lanes is approximately a number of lanes times a transmission rate of 10GBASE-KR in IEEE 802.3ap (2007).

11. The apparatus of claim 10, wherein:

each lane comprises a physical lane and each physical lane carries at least one virtual lane and

the FEC encoder and FEC decoder operate on each virtual lane independently.

12. The apparatus of claim 10, wherein

the FEC decoder logic is to indicate to the PCS sublayer logic errors in at least every alternate 64B/66B block sync bits.

13. The apparatus of claim 10 further comprising:

reverse gearbox logic configured to receive a 1-bit wide stream from the PCS sublayer logic and convert the stream to 66-bit wide 64B/66B blocks for the FEC encoder logic.

14. The apparatus of claim 10, wherein the FEC decoder logic is to provide 64B/66B blocks in a 1-bit wide stream to the PCS sublayer logic.

15. The apparatus of claim 10, further comprising:

logic to transmit a 48-bit auto-negotiation base page to a link partner, wherein the base page includes a Technology Ability field to indicate PHY types, FEC capability, Pause ability, and Remote fault, and Technology Ability bits in space A3 to indicate 40GBASE-KR4 ability.

16. The apparatus of claim 10, further comprising:

logic to transmit a 48-bit auto-negotiation base page to a link partner, wherein the base page includes a Technology Ability field to indicate PHY types, FEC capability, Pause ability, and Remote fault, and Technology Ability bits in space A4 to indicate 40GBASE-CR4 ability.

17. The apparatus of claim 10, further comprising:

logic to transmit a 48-bit auto-negotiation base page to a link partner, wherein the base page includes a Technology Ability field to indicate PHY types, FEC capability, Pause ability, and Remote fault, and Technology Ability bits in space A5 to indicate 100GBASE-CR10 ability.

18. The apparatus of claim 10, wherein:

a sum of transmit and receive delay contributed by the FEC layer logic is not more than 24576 BT.

19. The apparatus of claim 10, wherein:

a sum of transmit and receive delay contributed by the FEC layer logic is not more than 122880 BT.