Methods and software for placement improvement based on global routing

• US 8,370,786 B1
• Filed: 05/31/2011
• Issued: 02/05/2013
• Est. Priority Date: 05/28/2010
• Status: Active Grant

• Current Assignee: Golden Gate Technology Incorporated
• Original Assignee: Golden Gate Technology Incorporated
• Inventors: Burstein, Michael
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US13/149,275
• Time in Patent Office: 616 Days
• Field of Search: 716/110, 716/111, 716/113, 716/119, 716/122, 716/123, 716/126, 716/129, 716/130, 716/132, 716/134
• US Class Current: 716/134
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Methods and software for placing or re-placing integrated circuit cells and routing or re-routing nets between the cells in an integrated circuit layout. The method includes selecting a region of the cells in the integrated circuit layout, selecting a cell within the selected region, locating a border point where a net coupled to the selected cell crosses a border of the selected region, and moving the selected cell within the selected region to improve a timing characteristic (e.g., a wire length, capacitance, or other characteristic of the net that affects timing or delay) of the net. The method and software advantageously improve the placement of cells and routing of wires around congested or reserved regions after global routing has been performed, without causing timing violations in other signal paths on the integrated circuit device, in a computationally efficient manner.

Claims

1. A method of placing or re-placing cells in an integrated circuit layout and routing or re-routing nets between said cells in said integrated circuit layout, said method comprising:

selecting a region of said integrated circuit layout;

selecting one of said cells within said selected region;

locating a border point where a net coupled to said selected cell crosses a border of said selected region; and

using computing hardware, moving said selected cell within said selected region to improve a timing characteristic of a portion of said coupled net between said selected cell and said border point.

2. The method of claim 1, wherein said timing characteristic comprises a wire length or capacitance of said portion of said coupled net.

3. The method of claim 1, wherein said selected cell is moved closer to said border point.

4. The method of claim 1, further comprising obtaining an initial placement and routing of said integrated circuit layout.

5. The method of claim 1, further comprising determining whether moving said selected cell causes a timing violation in one or more signal paths of said integrated circuit layout that do not include said net.

6. The method of claim 5, further comprising determining one or more boundary characteristics for nets in said one or more signal paths.

7. The method of claim 6, wherein determining whether moving said selected cell causes timing violations comprises:

calculating one or more new characteristics for affected nets in said one or more signal paths after moving said selected cell; and

determining whether said new characteristic(s) are within said boundary characteristic(s) for said affected nets.

8. The method of claim 1, further comprising:

dividing said integrated circuit layout into a first plurality of regions, wherein said selected region comprises one of said first plurality of regions; and

after moving said selected cell, dividing said integrated circuit layout into a second plurality of regions and repeating locating said border point and moving steps for said selected cell in a new region selected from the second plurality of regions.

9. The method of claim 1, wherein said coupled net violates a timing constraint and is coupled to a second cell not in said selected region.

10. A method of re-placing integrated circuit cells and re-routing nets between said cells in an integrated circuit layout, said method comprising:

selecting a subset of said nets, wherein said nets in said subset violate a timing constraint; and

performing the method of claim 1 for each of said nets in said subset.

11. A non-transitory computer readable medium comprising a tangible computer executable set of instructions adapted to place or re-place cells in an integrated circuit layout and routing or re-routing nets between said cells in said integrated circuit layout, said instructions being adapted to:

select a region of said integrated circuit layout;

select one of said cells within said selected region;

locate a border point where a net coupled to said selected cell crosses a border of said selected region; and

move said selected cell within said selected region to improve a timing characteristic of a portion of said coupled net between said selected cell and said border point.

12. The computer readable medium of claim 11, wherein said timing characteristic comprises a wire length or capacitance of said portion of said coupled net.

13. The computer readable medium of claim 11, further comprising one or more instructions adapted to obtain an initial placement and routing of said integrated circuit layout.

14. The computer readable medium of claim 11, further comprising one or more instructions adapted to determine whether moving said selected cell causes a timing violation in one or more signal paths of said integrated circuit layout that do not include said net.

15. The computer readable medium of claim 14, further comprising instructions adapted to apply one or more boundary characteristics to nets in said one or more signal paths.

16. The computer readable medium of claim 15, wherein said boundary characteristic(s) comprise a maximum capacitance or a maximum length.

17. The computer readable medium of claim 15, wherein determining whether moving said selected cell causes timing violations comprises:

calculating one or more new characteristics for affected nets in said one or more signal paths after moving said selected cell; and

determining whether said new characteristic(s) are within said boundary characteristic(s) for said affected nets.

18. The computer readable medium of claim 11, further comprising instructions adapted to divide said integrated circuit layout into a first plurality of regions, wherein said selected region comprises one of said first plurality of regions.

19. The computer readable medium of claim 18, further comprising one or more instructions adapted to, after moving said selected cell, divide said integrated circuit layout into a second plurality of regions and repeat locating said border point and moving steps for said selected cell in a new region selected from the second plurality of regions.

20. The computer readable medium of claim 11, wherein said coupled net violates a timing constraint and is coupled to a second cell not in said selected region.