Device structure and manufacturing method using HDP deposited using deposited source-body implant block

• US 8,372,708 B2
• Filed: 10/04/2011
• Issued: 02/12/2013
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: Anup Bhalla, Francois Hebert, Sik K. Lui, Sung-Shan Tai
• Original Assignee: Francois Hebert
• Inventors: Bhalla, Anup, Hbert, Franois, Tai, Sung-Shan, Lui, Sik K
• Primary Examiner(s): Matthews, Colleen
• Assistant Examiner(s): YUSHINA, GALINA G
• Application Number:
  US13/200,869
• Publication Number:
  US 20120018793A1
• Time in Patent Office: 497 Days
• Field of Search: 438/270, 438/268, 438/272, 438/138, 438/197, 438/206, 438/438, 438/478, 438/498, 438/499, 438/506, 438/531, 438/546, 257/E21.258
• US Class Current: 438/206
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

Claims

1. A method for manufacturing a trenched semiconductor power device comprising;

opening a plurality of trenches from a top surface of a semiconductor substrate and forming a thick insulation layer covering over trench sidewalls and a bottom surface of said trenches and also simultaneously covering over the top surface of the semiconductor substrate outside of the trenches; and

applying an implanting-ion block mask for etching the thick insulation layer from a top part of the trenches and the trench sidewalls and also simultaneously from an area surrounding the trenches thus leaving a thick bottom insulation layer at a bottom portion of the trenches and implanting-ion blocks above said top surface in a mesa area at a distance away from said trenches and in a middle portion between two of said trenches for blocking body implanting ions and source ions from entering into said substrate under said mesa area whereby masks for manufacturing said semiconductor power device can be reduced.

2. The method of claim 1 wherein:

said step of forming said thick insulation layer further comprising a step of forming an oxide layer having a thickness larger than 0.3 microns.

3. The method of claim 1 wherein:

said step of forming said thick insulation layer further comprising a step of applying a chemical vapor deposition (CVD) to form an oxide layer covering over trench sidewalls and the bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches.

4. The method of claim 1 wherein:

said step of forming said thick insulation layer further comprising a step of applying a thermal oxidation to form an oxide layer covering over trench sidewalls and the bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches.

5. The method of claim 1 wherein:

said step of forming said thick insulation layer further comprising a step of applying a high-density plasma (HDP) deposition process to deposit an oxide layer covering over trench sidewalls and the bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches.

6. The method of claim 1 wherein:

said step of forming said thick insulation layer further comprising a step of applying a high-density plasma (HDP) deposition process for depositing a thick oxide layer covering bottom surface of said trenches and also covering over the top surface of the semiconductor substrate outside of the trenches having a thickness larger than 0.3 microns and greater than a thickness of the insulation layer covering the trench sidewalls.

7. The method of claim 1 further comprising:

implanting body ions into said semiconductor substrate with said implanting-ion block blocking said mesa area and diffusing said body ions into a body region with said body region separated as two separated body regions disposed on two opposite sides of said trenches.

8. The method of claim 1 further comprising:

implanting body ions into said semiconductor substrate with said implanting-ion block blocking said mesa area in the middle portion between two of said trenches and diffusing said body ions into a merged body region with said body region merged from two separated body regions disposed on two opposite sides of said implanting-ion block wherein said merged body region forming an inverted V pinnacle point near a bottom center of said merged body region.

9. The method of claim 1 further comprising:

implanting-ion block blocking said mesa area in the middle portion between two of said trenches and diffusing said body ions into a merged body region with said body region merged from two separated body regions disposed on two opposite sides of said implanting-ion block wherein said merged body region forming an inverted V pinnacle point near a bottom center of said merged body region; and

configuring said semiconductor power device by controlling a width between two of the trenches, a depth and a dopant concentration of the body region to generate a high electric filed to have a lowest breakdown voltage near said inverted V pinnacle point for inducing a breakdown near a bottom of said body region.

10. The method of claim 1 wherein:

forming said implanting-ion blocks in a termination area with a greater width than said implanting-ion block on said mesa area for separating body ion implanting regions to form floating body regions in said termination area thus form at least a guard ring in a trench surrounded by said floating body region in said termination area.

11. The method of claim 1 further comprising:

implanting and diffusing body and source ions with said implanting ion blocks in said mesa area to form body and source regions surrounding said trenches; and

etching off a portion of said implanting ion blocks for implanting body dopant ions with a higher dopant concentration than said body region to form high-concentration body dopant regions between said source regions and said body regions to form an integrated Schottky field effect transistor (FET).

12. The method of claim 1 further comprising:

forming trenched gate in each of said trenches as a split gate including a lower gate segment covered by an insulation layer and an upper gate segment above said insulation layer.

13. The method of claim 1 further comprising:

applying a HDP deposition process to form a thick oxide layer on bottom surface of said trenches simultaneously with and implanting ion blocks as HDP oxide layer and forming split gate in each of said trenches.

14. The method of claim 1 further comprising:

filling the trenches with a gate material to form trench gates and forming body regions and source regions by implanting body ions and source ions into said semiconductor substrate with said implanting-ion block blocking said mesa area in the middle portion between two of said trenches; and

forming an insulation protective layer on top of said semiconductor power device and opening a plurality of contact openings therethrough and extending to a body region; and

implanting a source-body ohmic contact dopant to form a source/body ohmic contact dopant region beneath each of said contact openings for enhancing ohmic contact to said body/source region.

15. The method of claim 14 further comprising:

manufacturing said semiconductor power device as a metal oxide semiconductor field effect transistor (MOSFET) device.

16. The method of claim 14 further comprising:

manufacturing said semiconductor power device as a N-channel metal oxide semiconductor field effect transistor (MOSFET) device.

17. The method of claim 14 further comprising:

manufacturing said semiconductor power device as a P-channel metal oxide semiconductor field effect transistor (MOSFET) device.