Vertical transistors

• US 8,372,710 B2
• Filed: 12/19/2011
• Issued: 02/12/2013
• Est. Priority Date: 09/01/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US13/329,977
• Publication Number:
  US 20120094449A1
• Time in Patent Office: 421 Days
• Field of Search: 438243-249, 438267-268, 438386-392, 257/E21.652, 257/E21.655
• US Class Current: 438/244
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A semiconductor structure having U-shaped transistors includes source/drain regions at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. Methods of forming semiconductor structures are also disclosed.

Claims

1. A method for forming a transistor for an integrated circuit, the method comprising:

forming a U-shaped silicon pillar pair connected by a base portion, wherein the silicon pillar pair comprises a first pillar and a second pillar, the first and second pillars each having an inner wall, first and second outer sidewalls and an end wall, wherein the inner walls of the first and second pillars face each other, the end walls of the first and second pillars face away from each other, and the outer sidewalls connect the inner and end walls of each of the first and second pillars, and wherein the base portion has a first outer sidewall coplanar with the first outer sidewalls of the first and second pillars, and a second outer sidewall coplanar with the second outer sidewalls of the first and second pillars;

forming a source region in the first pillar;

forming a drain region in the second pillar; and

forming a first gate line facing the first outer sidewalls of the first pillar, second pillar, and base portion, wherein the source region, the drain region, and at least a portion of the gate line form a U-shaped transistor.

2. The method of claim 1 further comprising filling a gap between the inner walls of the first and second pillars with a dielectric layer.

3. The method of claim 1 further comprising forming a metal layer on the gate line and performing a self-aligned salicide process on the metal layer.

4. The method of claim 1 further comprising forming a second gate line facing the second outer sidewalls of the first and second pillars.

5. A method for forming a semiconductor device, the method comprising:

etching a first trench to a first depth into a semiconductor substrate;

etching two second trenches to a second depth into the semiconductor substrate, wherein the first trench is substantially parallel to the second trenches, and wherein the first trench is positioned in between two second trenches within the semiconductor substrate;

etching two third trenches to a third depth into the semiconductor substrate, wherein the third trenches are substantially orthogonal to the first trench and to the second trenches;

wherein the first, second, and third trenches define a first vertically extending pillar comprising a vertical source region and a second vertically extending pillar comprising a vertical drain region, and wherein the third depth is greater than the first depth and less than the second depth; and

forming a gate line within at least a portion of one of the third trenches, wherein the gate line, the vertical source region, and the vertical drain region form a U-shaped transistor in which the vertical source region and the vertical drain region are connected to one another through a transistor channel.

6. The method of claim 5 further comprising filling at least a portion of the first trenches with an oxide-containing material.

7. The method of claim 5 further comprising filling at least a portion of the first trenches with a conductive gate material.

8. The method of claim 5 further comprising filling at least a portion of the second trench with an oxide-containing material.

9. The method of claim 5, wherein the gate line comprises a gate electrode layer and a metallic layer.

10. The method of claim 9, wherein the metallic layer comprises a metal silicide.

11. The method of claim 5, wherein the transistor comprises the vertical source region electrically connected to a digit line and the vertical drain region electrically connected to a memory storage device.

12. The method of claim 5, wherein the first trenches and the second trench are etched prior to etching the third set of trenches.

13. A method for forming a memory array, the method comprising:

forming a first set of trenches in a semiconductor substrate;

forming a second set of trenches in the semiconductor substrate, the second set of trenches substantially parallel to the first set;

forming a third set of trenches in the semiconductor substrate, the third set of trenches intersecting with the paths of the first and second sets of trenches;

wherein the trenches define pairs of pillars comprising U-shaped transistors, wherein each pillar in the pair of pillars is separated by one trench of the first set of trenches, and wherein each U-shaped transistor is separated from an adjacent U-shaped transistor by one trench of the second set of trenches, and wherein each of the transistors comprises a drain region at the top of one pillar and a source region at the top of the other pillar.

14. The method of claim 13 further comprising forming an epitaxial silicon layer on the semiconductor substrate prior to forming the first set of trenches.

15. The method of claim 13 further comprising forming a gate line in at least a portion of the third set of trenches.

16. The method of claim 13, further comprising:

electrically connecting a digit line to the source region of each of the transistors; and

electrically connecting a memory storage device to the drain region of each of the transistors.

17. The method of claim 13, wherein a column of the U-shaped transistors surrounded by the gate line in the trenches of the third set of trenches on either side of the column form a wordline.

18. The method of claim 17, wherein the memory storage device is a capacitor.

19. A method of forming a semiconductor structure comprising:

forming a set of wordline trenches within a semiconductor substrate;

forming a set of deep trenches within a semiconductor substrate, the set of deep trenches crossing and creating a grid with the set of wordline trenches, wherein the deep trenches are deeper than the wordline trenches, and wherein the set of wordline trenches and the set of deep trenches define a plurality of protrusions within the semiconductor substrate;

forming a shallow trench into each protrusion to form a U-shaped protrusion comprising a first pillar, a second pillar, and a base, wherein the shallow trench is substantially parallel to the set of deep trenches

defining a source region in the first pillar and a drain region in the second pillar within each U-shaped protrusion;

depositing gate material into the set of wordline trenches; and

spacer etching the gate material to define a gate electrode on sidewalls of the U-shaped protrusion.

20. The method of claim 19, wherein the gate electrode is only formed on opposite sidewalls of the U-shaped protrusion.

21. The method of claim 19, wherein defining source region and the drain region comprises doping the semiconductor substrate prior to etching.