Semiconductor device and manufacturing method thereof

• US 8,373,164 B2
• Filed: 11/06/2009
• Issued: 02/12/2013
• Est. Priority Date: 11/07/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Akimoto, Kengo, Kawae, Daisuke
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): JOY, JEREMY J
• Application Number:
  US12/613,769
• Publication Number:
  US 20100117077A1
• Time in Patent Office: 1,194 Days
• Field of Search: 257/43, 257/57, 257/E21.459, 257/E29.296, 257/59, 257/72, 257/E29.277, 257/E21.535, 438/104, 438/158, 438/149
• US Class Current: 257/57
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/84 Ohmic electrodes, e.g. source or drain electrodes

Abstract

A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Claims

1. A semiconductor device comprising:

a gate electrode over a substrate having an insulating surface;

an insulating layer over the gate electrode;

a source electrode and a drain electrode over the insulating layer; and

an oxide semiconductor layer between a side surface of the source electrode and a side surface of the drain electrode, which face each other, so as to overlap with the gate electrode with the insulating layer interposed therebetween,

wherein the oxide semiconductor layer is in contact with at least one of the side surface of the source electrode and the side surface of the drain electrode,

wherein a first angle between a surface of the substrate and a side surface of a first bottom edge of the source electrode and a second angle between the surface of the substrate and a side surface of a second bottom edge of the drain electrode are each greater than or equal to 20° and

less than 90°

,

wherein the first angle is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the source electrode, and

wherein the second angle is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the drain electrode.

2. The semiconductor device according to claim 1, wherein the side surface of each of the source electrode and the drain electrode has a curved surface at least partly.

3. The semiconductor device according to claim 1, further comprising a buffer layer over the source electrode and the drain electrode,

wherein the oxide semiconductor layer is over the buffer layer.

4. The semiconductor device according to claim 1, wherein a first region of the oxide semiconductor layer, which overlaps with the side surface of the source electrode and a second region of the oxide semiconductor layer, which overlaps with the side surface of the drain electrode are electric-field relaxation regions.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises at least one material selected from the group consisting of indium, gallium, and zinc.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a gate insulating layer to cover the gate electrode;

forming a conductive layer and a first oxide semiconductor layer over the gate insulating layer without exposure to air;

etching the conductive layer and the first oxide semiconductor layer to form a source electrode and a drain electrode each having a side surface which forms an angle greater than or equal to 20° and

less than 90°

with respect to a surface of the substrate, and a buffer layer; and

forming a second oxide semiconductor layer over the gate insulating layer, the source electrode, and the drain electrode,

wherein the side surface of each of the source electrode and the drain electrode has a step.

7. The method for manufacturing the semiconductor device according to claim 6, wherein each of the buffer layer and the second oxide semiconductor layer comprises at least one material selected from the group consisting of indium, gallium, and zinc.

8. The method for manufacturing the semiconductor device according to claim 6, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are each formed using a target having the same composition.

9. The method for manufacturing the semiconductor device according to claim 6, wherein a first region of the second oxide semiconductor layer, which overlaps with the side surface of the source electrode and a second region of the second oxide semiconductor layer, which overlaps with the side surface of the drain electrode are electric-field relaxation regions.

10. The method for manufacturing the semiconductor device according to claim 6, wherein the side surface of each of the source electrode and the drain electrode has a curved surface at least partly.

11. The method for manufacturing the semiconductor device according to claim 6, wherein the side surface of each of the source electrode and the drain electrode has a shape that spreads toward the substrate from a top surface of each of the source electrode and the drain electrode.

12. The method for manufacturing the semiconductor device according to claim 6, wherein the second oxide semiconductor layer has lower resistance than the buffer layer.

13. A semiconductor device comprising:

a gate electrode over a substrate having an insulating surface;

an insulating layer over the gate electrode;

a source electrode and a drain electrode over the insulating layer; and

an oxide semiconductor layer between a side surface of the source electrode and a side surface of the drain electrode, which face each other, so as to overlap with the gate electrode with the insulating layer interposed therebetween,

wherein the oxide semiconductor layer is in contact with at least one of the side surface of the source electrode and the side surface of the drain electrode,

wherein the side surface of each of the source electrode and the drain electrode has a step, and

wherein a first angle between a surface of the substrate and a side surface of a first bottom edge of the source electrode and a second angle between the surface of the substrate and a side surface of a second bottom edge of the drain electrode are each greater than or equal to 20° and

less than 90°

.

14. The semiconductor device according to claim 13, wherein the first angle is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the source electrode.

15. The semiconductor device according to claim 13, wherein the second angle is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the drain electrode.

16. The semiconductor device according to claim 13, wherein the side surface of each of the source electrode and the drain electrode has a curved surface at least partly.

17. The semiconductor device according to claim 13, further comprising a buffer layer over the source electrode and the drain electrode,

wherein the oxide semiconductor layer is over the buffer layer.

18. The semiconductor device according to claim 13, wherein a first region of the oxide semiconductor layer, which overlaps with the side surface of the source electrode and a second region of the oxide semiconductor layer, which overlaps with the side surface of the drain electrode are electric-field relaxation regions.

19. The semiconductor device according to claim 13, wherein the oxide semiconductor layer comprises at least one material selected from the group consisting of indium, gallium, and zinc.

20. A semiconductor device comprising:

a gate electrode over a substrate having an insulating surface;

an insulating layer over the gate electrode;

a source electrode and a drain electrode over the insulating layer; and

an oxide semiconductor layer between a side surface of the source electrode and a side surface of the drain electrode with the insulating layer interposed therebetween,

wherein the oxide semiconductor layer is in contact with the side surface of the source electrode and the side surface of the drain electrode,

wherein the side surface of the each of the source electrode and the drain electrode has a shape that spreads toward the substrate from a top surface of each of the source electrode and the drain electrode,

wherein the side surface of each of the source electrode and the drain electrode has a step, and

wherein a first angle between a surface of the substrate and a side surface of a first bottom edge of the source electrode and a second angle between the surface of the substrate and a side surface of a second bottom edge of the drain electrode are each greater than or equal to 20° and

less than 90°

.

21. The semiconductor device according to claim 20, wherein the first angle is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the source electrode.

22. The semiconductor device according to claim 20, wherein the second angle is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the drain electrode.

23. The semiconductor device according to claim 21, further comprising a buffer layer over the source electrode and the drain electrode,

wherein the oxide semiconductor layer is over the buffer layer.

24. The semiconductor device according to claim 21, wherein a first region of the oxide semiconductor layer, which overlaps with the side surface of the source electrode and a second region of the oxide semiconductor layer, which overlaps with the side surface of the drain electrode are electric-field relaxation regions.

25. The semiconductor device according to claim 21, wherein the oxide semiconductor layer comprises at least one material selected from the group consisting of indium, gallium, and zinc.

26. A semiconductor device comprising:

a gate electrode over a substrate having an insulating surface;

an insulating layer over the gate electrode;

a source electrode and a drain electrode over the insulating layer; and

an oxide semiconductor layer between a side surface of the source electrode and a side surface of the drain electrode with the insulating layer interposed therebetween,

wherein the oxide semiconductor layer is in contact with the side surface of the source electrode and the side surface of the drain electrode,

wherein the side surface of the each of the source electrode and the drain electrode has a shape that spreads toward the substrate from a top surface of each of the source electrode and the drain electrode,

wherein a first angle between a surface of the substrate and a side surface of a first bottom edge of the source electrode and a second angle between the surface of the substrate and a side surface of a second bottom edge of the drain electrode are each greater than or equal to 20° and

less than 90°

,

wherein the first angle is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the source electrode, and

wherein the second angle is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the drain electrode.

27. The semiconductor device according to claim 26, further comprising a buffer layer over the source electrode and the drain electrode,

wherein the oxide semiconductor layer is over the buffer layer.

28. The semiconductor device according to claim 26, wherein a first region of the oxide semiconductor layer, which overlaps with the side surface of the source electrode and a second region of the oxide semiconductor layer, which overlaps with the side surface of the drain electrode are electric-field relaxation regions.

29. The semiconductor device according to claim 26, wherein the oxide semiconductor layer comprises at least one material selected from the group consisting of indium, gallium, and zinc.

30. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate having an insulating surface;

forming a gate insulating layer to cover the gate electrode;

forming a conductive layer and a first oxide semiconductor layer over the gate insulating layer without exposure to air;

etching the conductive layer and the first oxide semiconductor layer to form a source electrode and a drain electrode each having a side surface which forms an angle greater than or equal to 20° and

less than 90°

with respect to a surface of the substrate, and a buffer layer; and

forming a second oxide semiconductor layer over the gate insulating layer, the source electrode, and the drain electrode,

wherein a first angle between the surface of the substrate and a side surface of a first bottom edge of the source electrode and a second angle between the surface of the substrate and a side surface of a second bottom edge of the drain electrode are each greater than or equal to 20° and

less than 90°

,

wherein the first angle is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the source electrode, and

wherein the second angle is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the drain electrode.

31. The method for manufacturing the semiconductor device according to claim 30, wherein each of the buffer layer and the second oxide semiconductor layer comprises at least one material selected from the group consisting of indium, gallium, and zinc.

32. The method for manufacturing the semiconductor device according to claim 30, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are each formed using a target having the same composition.

33. The method for manufacturing the semiconductor device according to claim 30, wherein a first region of the second oxide semiconductor layer, which overlaps with the side surface of the source electrode and a second region of the second oxide semiconductor layer, which overlaps with the side surface of the drain electrode are electric-field relaxation regions.

34. The method for manufacturing the semiconductor device according to claim 30, wherein the side surface of each of the source electrode and the drain electrode has a curved surface at least partly.

35. The method for manufacturing the semiconductor device according to claim 30, wherein the side surface of each of the source electrode and the drain electrode has a shape that spreads toward the substrate from a top surface of each of the source electrode and the drain electrode.

36. The method for manufacturing the semiconductor device according to claim 30, wherein the second oxide semiconductor layer has lower resistance than the buffer layer.

37. A semiconductor device comprising:

a transistor comprising;

a gate electrode, an insulating layer, an oxide semiconductor layer, a source electrode, and a drain electrode over a substrate, wherein the insulating layer is between the gate electrode and the oxide semiconductor layer, and

wherein the oxide semiconductor layer is in contact with the source electrode and the drain electrode,

wherein a first angle between a surface of the substrate and a side surface of a first bottom edge of the source electrode is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the source electrode, and

wherein a second angle between the surface of the substrate and a side surface of a second bottom edge of the drain electrode is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the drain electrode.

38. The semiconductor device according to claim 37, wherein the transistor is a bottom gate transistor.

39. The semiconductor device according to claim 37, wherein the side surface of each of the source electrode and the drain electrode has a curved surface at least partly.

40. The semiconductor device according to claim 37, further comprising a buffer layer.

41. The semiconductor device according to claim 37, wherein a first region of the oxide semiconductor layer, which overlaps with the side surface of the source electrode and a second region of the oxide semiconductor layer, which overlaps with the side surface of the drain electrode and electric-field relaxation regions.

42. The semiconductor device according to claim 37, wherein the oxide semiconductor layer comprises at least one material selected from the group consisting of indium, gallium, and zinc.

49. The semiconductor device according to claim 37, wherein the oxide semiconductor layer is formed over the source electrode and the drain electrode.

43. A method for manufacturing a semiconductor device, comprising the steps of:

forming a transistor comprising a gate electrode, an insulating layer, an oxide semiconductor layer, a source electrode, and a drain electrode over a substrate,

wherein the insulating layer is between the gate electrode and the oxide semiconductor layer,

wherein the oxide semiconductor layer is in contact with the source electrode and the drain electrode, and

wherein a first angle between a surface of the substrate and a side surface of a first bottom edge of the source electrode is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the source electrode, and

wherein a second angle between the surface of the substrate and a side surface of a second bottom edge of the drain electrode is made to be different from an angle between the surface of the substrate and a side surface of a top edge of the drain electrode.

44. The method for manufacturing the semiconductor device according to claim 43, wherein the transistor is a bottom gate transistor.

45. The method for manufacturing the semiconductor device according to claim 43, wherein the oxide semiconductor layer comprises at least one material selected from the group consisting of indium, gallium, and zinc.

46. The method for manufacturing the semiconductor device according to claim 43, wherein a first region of the oxide semiconductor layer, which overlaps with the side surface of the source electrode and a second region of the oxide semiconductor layer, which overlaps with the side surface of the drain electrode are electric-field relaxation regions.

47. The method for manufacturing the semiconductor device according to claim 43, wherein the side surface of the each of the source electrode and the drain electrode has a curved surface at least partly.

48. The method for manufacturing the semiconductor device according to claim 43, wherein the side surface of the each of the source electrode and the drain electrode has a shape that spreads toward the substrate from a top surface of each of the source electrode and the drain electrode.

50. The method for manufacturing the semiconductor device according to claim 43, wherein the oxide semiconductor layer is formed over the source electrode and the drain electrode.