Semiconductor device

• US 8,373,203 B2
• Filed: 11/24/2010
• Issued: 02/12/2013
• Est. Priority Date: 11/27/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Godo, Hiromichi, Kawae, Daisuke
• Primary Examiner(s): HOANG, QUOC DINH
• Application Number:
  US12/954,222
• Publication Number:
  US 20110127525A1
• Time in Patent Office: 811 Days
• Field of Search: 257/43, 257/227, 257/291, 257/292, 257/439, 257/665, 257/E29.151, 438/151
• US Class Current: 257/227
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×10¹²/cm³ is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm an inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer adjacent to the gate electrode layer; and

an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween,

wherein a carrier concentration of the oxide semiconductor layer is less than 1×

10¹²/cm³,

wherein a length of a channel formed in the oxide semiconductor layer is 0.2 μ

m to 3.0 μ

m,

wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm, and

wherein a thickness of the gate insulating layer is 20 nm to 50 nm.

2. The semiconductor device according to claim 1, wherein the gate electrode layer comprises a film containing a metal element selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium as its main component;

an alloy film;

or a stack of any of these films.

3. The semiconductor device according to claim 1, wherein the gate insulating layer comprises a single-layer film or a laminate film of any of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, and tantalum oxide.

4. An electronic device comprising the semiconductor device according to claim 1.

5. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer adjacent to the gate electrode layer; and

an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween,

wherein a carrier concentration of the oxide semiconductor layer is less than 1×

10¹²/cm³,

wherein a length of a channel formed in the oxide semiconductor layer is 0.2 μ

m to 3.0 μ

m,

wherein a thickness of the oxide semiconductor layer is 15 nm to 100 nm, and

wherein a thickness of the gate insulating layer is 10 nm to 20 nm.

6. The semiconductor device according to claim 5, wherein the gate electrode layer comprises a film containing a metal element selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium as its main component;

an alloy film;

or a stack of any of these films.

7. The semiconductor device according to claim 5, wherein the gate insulating layer comprises a single-layer film or a laminate film of any of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, and tantalum oxide.

8. An electronic device comprising the semiconductor device according to claim 5.

9. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping the gate electrode layer with the gate insulating layer therebetween;

source and drain electrode layers over the oxide semiconductor layer, the source and drain electrode layers overlapping parts of the oxide semiconductor layer; and

an oxide insulating layer over the source and drain electrode layers, the oxide insulating layer being in contact with the oxide semiconductor layer,

wherein a carrier concentration of the oxide semiconductor layer is less than 1×

10¹²/cm³,

wherein a length of a channel formed in the oxide semiconductor layer is 0.2 μ

m to 3.0 μ

m,

wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm, and

wherein a thickness of the gate insulating layer is 20 nm to 50 nm.

10. The semiconductor device according to claim 9, wherein the gate electrode layer comprises a film containing a metal element selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium as its main component;

an alloy film;

or a stack of any of these films.

11. The semiconductor device according to claim 9, wherein the source and drain electrode layers comprise a film containing a metal element selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium as its main component;

an alloy film;

or a stack of any of these films.

12. The semiconductor device according to claim 9, wherein the gate insulating layer comprises a single-layer film or a laminate film of any of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, and tantalum oxide.

13. The semiconductor device according to claim 9, wherein the oxide insulating layer comprises an inorganic insulating film selected from a silicon oxide, a silicon nitride oxide, an aluminum oxide, and an aluminum oxynitride.

14. An electronic device comprising the semiconductor device according to claim 9.

15. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping the gate electrode layer with the gate insulating layer therebetween;

source and drain electrode layers over the oxide semiconductor layer, the source and drain electrode layers overlapping parts of the oxide semiconductor layer; and

an oxide insulating layer over the source and drain electrode layers, the oxide insulating layer being in contact with the oxide semiconductor layer,

wherein a carrier concentration of the oxide semiconductor layer is less than 1×

10¹²/cm³,

wherein a length of a channel formed in the oxide semiconductor layer is 0.2 μ

m to 3.0 μ

m,

wherein a thickness of the oxide semiconductor layer is 15 nm to 100 nm, and

wherein a thickness of the gate insulating layer is 10 nm to 20 nm.

16. The semiconductor device according to claim 15, wherein the gate electrode layer comprises a film containing a metal element selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium as its main component;

an alloy film;

or a stack of any of these films.

17. The semiconductor device according to claim 15, wherein the source and drain electrode layers comprise a film containing a metal element selected from aluminum, copper, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, and scandium as its main component;

an alloy film;

or a stack of any of these films.

18. The semiconductor device according to claim 15, wherein the gate insulating layer comprises a single-layer film or a laminate film of any of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, and tantalum oxide.

19. The semiconductor device according to claim 15, wherein the oxide insulating layer comprises an inorganic insulating film selected from a silicon oxide, a silicon nitride oxide, an aluminum oxide, and an aluminum oxynitride.

20. An electronic device comprising the semiconductor device according to claim 15.

21. A semiconductor device comprising a first transistor and a second transistor, each of the first transistor and the second transistor comprising:

a gate electrode layer;

a gate insulating layer adjacent to the gate electrode layer; and

an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween,

wherein a carrier concentration of the oxide semiconductor layer is less than 1×

10¹²/cm³,

wherein a length of a channel formed in the oxide semiconductor layer is 0.2 μ

m to 3.0 μ

m,

wherein a thickness of the oxide semiconductor layer is 15 nm to 30 nm,

wherein a thickness of the gate insulating layer is 20 nm to 50 nm, and

wherein a difference in threshold voltage between the first transistor and the second transistor is less than 0.5 V.

22. A semiconductor device comprising a first transistor and a second transistor, each of the first transistor and the second transistor comprising:

a gate electrode layer;

a gate insulating layer adjacent to the gate electrode layer; and

an oxide semiconductor layer adjacent to the gate electrode layer with the gate insulating layer therebetween,

wherein a carrier concentration of the oxide semiconductor layer is less than 1×

10¹²/cm³,

wherein a length of a channel formed in the oxide semiconductor layer is 0.2 μ

m to 3.0 μ

m,

wherein a thickness of the oxide semiconductor layer is 5 nm to 100 nm,

wherein a thickness of the gate insulating layer is 10 nm to 20 nm, and

wherein a difference in threshold voltage between the first transistor and the second transistor is less than 0.5 V.