Lateral super junction device with high substrate-gate breakdown and built-in avalanche clamp diode

• US 8,373,208 B2
• Filed: 04/30/2010
• Issued: 02/12/2013
• Est. Priority Date: 11/30/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur, Guan, Lingpeng, Bhalla, Anup, Yilmaz, Hamza
• Primary Examiner(s): DIALLO, MAMADOU L
• Application Number:
  US12/799,810
• Publication Number:
  US 20110127586A1
• Time in Patent Office: 1,019 Days
• Field of Search: 257/328, 257/262, 257/337
• US Class Current: 257/262
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0843 Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/7817 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7821 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

Claims

1. A semiconductor power device comprising:

a semiconductor substrate including a super junction structure disposed near a top surface of said semiconductor substrate wherein said super junction structure comprising a plurality of laterally stacked layers of alternating conductivity types of a first and second conductivity types extending laterally from a source column to a drain column wherein said source column and drain column are of a first conductivity type and extend downward through said super-junction structure; and

a gate column of a second conductivity type extending downward through said super junction structure for applying a voltage on the super junction structure to control a current transmitted laterally through said super junction structure between said source and said drain columns;

the semiconductor substrate further comprises a bottom semiconductor layer of a first conductivity type, wherein said drain column extends downwardly to connect to said bottom semiconductor layer;

the semiconductor substrate further comprises an intermediate semiconductor layer of a second conductivity type disposed under said super junction structure and on top of said bottom semiconductor layer; and

the gate column extends downwardly into the intermediate semiconductor layer to constitute a built-in gate-drain avalanche clamp diode from a combination of the bottom semiconductor layer through the intermediate semiconductor layer to the gate column.

2. A semiconductor power device comprising:

a semiconductor substrate including a super junction structure disposed near a top surface of said semiconductor substrate wherein said super junction structure comprising a plurality of laterally stacked layers of alternating conductivity types of a first and second conductivity types extending laterally from a source column to a drain column wherein said source column and drain column are of a first conductivity type and extend downward through said super-junction structure; and

a gate column of a second conductivity type extending downward through said super junction structure for applying a voltage on the super junction structure to control a current transmitted laterally through said super junction structure between said source and said drain columns;

the semiconductor substrate further comprises a bottom semiconductor layer of a first conductivity type, wherein said drain column extends downwardly to connect to said bottom semiconductor layer;

the semiconductor substrate further comprises an intermediate semiconductor layer of a second conductivity type disposed under said super junction structure and on top of said bottom semiconductor layer; and

the source column extends into said intermediate semiconductor layer and further comprises a bipolar suppressing region in the intermediate semiconductor layer at the bottom of the source column;

said bipolar suppressing region is doped with the second conductivity type.

3. A semiconductor power device comprising:

a semiconductor substrate including a super junction structure disposed near a top surface of said semiconductor substrate wherein said super junction structure comprising a plurality of laterally stacked layers of alternating conductivity types of a first and second conductivity types extending laterally from a source column to a drain column wherein said source column and drain column are of a first conductivity type and extend downward through said super-junction structure; and

a gate column of a second conductivity type extending downward through said super junction structure for applying a voltage on the super junction structure to control a current transmitted laterally through said super junction structure between said source and said drain columns;

the semiconductor substrate further comprises a bottom semiconductor layer of a first conductivity type, wherein said drain column extends downwardly to connect to said bottom semiconductor layer;

the semiconductor substrate further comprises an intermediate semiconductor layer of a second conductivity type disposed under said super junction structure and on top of said bottom semiconductor layer; and

the gate column extends deeper than the source column.

4. A semiconductor power device comprising:

a semiconductor substrate including a super junction structure disposed near a top surface of said semiconductor substrate wherein said super junction structure comprising a plurality of laterally stacked layers of alternating conductivity types of a first and second conductivity types extending laterally from a source column to a drain column wherein said source column and drain column are of a first conductivity type and extend downward through said super-junction structure; and

a gate column of a second conductivity type extending downward through said super junction structure for applying a voltage on the super junction structure to control a current transmitted laterally through said super junction structure between said source and said drain columns;

the semiconductor substrate further comprises a bottom semiconductor layer of a first conductivity type, wherein said drain column extends downwardly to connect to said bottom semiconductor layer;

the semiconductor substrate further comprises an intermediate semiconductor layer of a second conductivity type disposed under said super junction structure and on top of said bottom semiconductor layer; and

said source, drain and gate columns form a JFET, and wherein the semiconductor power device further comprises a MOSFET connected in a cascode circuit configuration with said JFET.

5. The semiconductor power device of claim 4 wherein:

said MOSFET is integrated with said JFET at the device cell level.

6. The device of claim 5, wherein:

said MOSFET further comprises a source region, a body region, a gate, and a drain region wherein the source region extends along a direction parallel to the source column and is separated therefrom with the body region disposed between the source region and the source column.

7. The device of claim 6 wherein

said gate of the MOSFET is configured to form an inversion channel between said source region of the MOSFET and said source column.

8. A semiconductor power device comprising:

a semiconductor substrate including a super junction structure disposed near a top surface of said semiconductor substrate wherein said super junction structure comprising a plurality of laterally stacked layers of alternating conductivity types of a first and second conductivity types extending laterally from a source column to a drain column wherein said source column and drain column are of a first conductivity type and extend downward through said super-junction structure; and

a gate column of a second conductivity type extending downward through said super junction structure for applying a voltage on the super junction structure to control a current transmitted laterally through said super junction structure between said source and said drain columns;

the semiconductor substrate further comprises a bottom semiconductor layer of a first conductivity type, wherein said drain column extends downwardly to connect to said bottom semiconductor layer;

the semiconductor substrate further comprises an intermediate semiconductor layer of a second conductivity type disposed under said super junction structure and on top of said bottom semiconductor layer; and

the source, drain and gate columns are arranged as stripes extending horizontally across the semiconductor substrate.

9. A semiconductor power device comprising:

a semiconductor substrate including a super junction structure disposed near a top surface of said semiconductor substrate wherein said super junction structure comprising a plurality of laterally stacked layers of alternating conductivity types of a first and second conductivity types extending laterally from a source column to a drain column wherein said source column and drain column are of a first conductivity type and extend downward through said super-junction structure; and

a gate column of a second conductivity type extending downward through said super junction structure for applying a voltage on the super junction structure to control a current transmitted laterally through said super junction structure between said source and said drain columns;

the semiconductor substrate further comprises a bottom semiconductor layer of a first conductivity type, wherein said drain column extends downwardly to connect to said bottom semiconductor layer;

the semiconductor substrate further comprises an intermediate semiconductor layer of a second conductivity type disposed under said super junction structure and on top of said bottom semiconductor layer; and

the source, drain and gate columns are formed with a closed cell layout configuration across a horizontal direction of the semiconductor substrate.

10. The semiconductor power device of claim 9 wherein:

the source column is formed along a closed cell in the closed cell layout configuration and the drain column is formed at the center of each cell.

11. A semiconductor power device comprising:

a semiconductor substrate including a super junction structure disposed near a top surface of said semiconductor substrate wherein said super junction structure comprising a plurality of laterally stacked layers of alternating conductivity types of a first and second conductivity types extending laterally from a source column to a drain column wherein said source column and drain column are of a first conductivity type and extend downward through said super-junction structure; and

a gate column of a second conductivity type extending downward through said super junction structure for applying a voltage on the super junction structure to control a current transmitted laterally through said super junction structure between said source and said drain columns;

the semiconductor substrate further comprises a bottom semiconductor layer of a first conductivity type, wherein said drain column extends downwardly to connect to said bottom semiconductor layer; and

the gate column is staggered alongside the source column.

12. A semiconductor power device comprising:

a semiconductor substrate including a super junction structure disposed near a top portion of the semiconductor substrate wherein said super junction structure comprising a plurality of laterally stacked layers of alternating conductivity types of a first and second conductivity types extending laterally from a source column to a drain column wherein said source column and drain column are of a first conductivity type and extend downward through said super-junction structure; and

a gate column of a second conductivity type extending downward through said super junction structure for applying a voltage on the super junction structure to control a current transmitted laterally through said super junction structure between said source and said drain columns; and

a built-in gate-drain avalanche clamp diode disposed near a bottom surface of said semiconductor substrate under one of said gate columns and said drain column.

13. The semiconductor power device of claim 12 further comprising:

a bottom semiconductor layer disposed under the super junction structure, wherein

one of said gate columns or said drain columns interfaces as a PN junction with said bottom semiconductor layer thus constitutes said built-in gate-drain avalanche clamp diode near the bottom surface of the semiconductor substrate.

14. The semiconductor power device of claim 13 wherein:

at least one of said gate columns and drain columns extends downwardly to electrically connect to said bottom semiconductor layer.