Logic circuit

• US 8,373,443 B2
• Filed: 05/26/2011
• Issued: 02/12/2013
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Akimoto, Kengo, Tsubuku, Masashi
• Primary Examiner(s): Ismail, Shawki
• Assistant Examiner(s): Tran, Jany
• Application Number:
  US13/116,372
• Publication Number:
  US 20110221475A1
• Time in Patent Office: 628 Days
• Field of Search: 257/268, 257/348
• US Class Current: 326/120
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H03K 19/094 using field-effect transistors
• CPC Class Codes: H03K 19/09407 of the same canal type
• CPC Class Codes: H03K 19/09421 Diode field-effect transistor logic H03K19/0956, H03K19/096 take precedence
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence

Abstract

An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.

Claims

1. A logic circuit comprising:

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode;

a first terminal electrically connected to the second gate electrode of the second transistor; and

a second terminal electrically connected to a portion where the second transistor is connected to the first transistor,

wherein a high power supply voltage terminal is electrically connected to one of the first source electrode and the first drain electrode of the first transistor, and the first gate electrode of the first transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor;

wherein one of the second source electrode and the second drain electrode of the second transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor, and a low power supply voltage terminal is electrically connected to the other of the second source electrode and the second drain electrode of the second transistor,

wherein the first transistor comprises;

the first gate electrode;

a gate insulating layer provided over the first gate electrode;

a first oxide semiconductor layer provided over the gate insulating layer;

the first source electrode which is electrically connected to the first oxide semiconductor layer; and

the first drain electrode which is electrically connected to the first oxide semiconductor layer,

wherein a reduction prevention layer does not overlap the first oxide semiconductor layer, the first source electrode, and the first drain electrode,

wherein the second transistor comprises;

the second gate electrode;

the gate insulating layer provided over the second gate electrode;

a second oxide semiconductor layer provided over the gate insulating layer;

the second source electrode which is electrically connected to the second oxide semiconductor layer; and

the second drain electrode which is electrically connected to the second oxide semiconductor layer,

wherein the reduction prevention layer overlaps the second oxide semiconductor layer, the second source electrode, and the second drain electrode.

2. The logic circuit according to claim 1, wherein the second transistor includes an oxygen vacancy control region between the second source electrode and the second drain electrode over a surface of the first oxide semiconductor layer, which is opposite to a surface in contact with the gate insulating layer.

3. The logic circuit according to claim 1, wherein the first transistor and the second transistor have the same conductivity type.

4. The logic circuit according to claim 1, wherein one of the second source electrode and the second drain electrode of the second transistor is in contact with the first gate electrode of the first transistor through an opening portion provided in the gate insulating layer.

5. The logic circuit according to claim 1,

wherein the first transistor does not include the reduction prevention layer over the first oxide semiconductor layer, the first source electrode, and the first drain electrode.

6. The logic circuit according to claim 1,

wherein the reduction prevention layer comprises one selected from the group of silicon oxide and aluminum oxide.

7. The logic circuit according to claim 1,

wherein the first transistor is a depletion transistor and the second transistor is an enhancement transistor.

8. The logic circuit according to claim 1,

wherein each of the first transistor and the second transistor further comprises a source region and a drain region in contact with part of the first oxide semiconductor layer, wherein the source region and the drain region are third oxide semiconductor layers.

9. The logic circuit according to claim 8,

wherein the third oxide semiconductor layers contain indium, gallium, and zinc.

10. A logic circuit comprising:

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode;

a first terminal electrically connected to the second gate electrode of the second transistor; and

a second terminal electrically connected to a portion where the second transistor is connected to the first transistor,

wherein a high power supply voltage terminal is electrically connected to one of the first source electrode and the first drain electrode of the first transistor, and the first gate electrode of the first transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor;

wherein one of the second source electrode and the second drain electrode of the second transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor, and a low power supply voltage terminal is electrically connected to the other of the second source electrode and the second drain electrode of the second transistor,

wherein the first transistor comprises;

the first gate electrode

a gate insulating layer provided over the first gate electrode;

a first oxide semiconductor layer provided over the gate insulating layer;

the first source electrode which is electrically connected to the first oxide semiconductor layer; and

the first drain electrode which is electrically connected to the first oxide semiconductor layer,

wherein a reduction prevention layer does not overlap the first oxide semiconductor layer, the first source electrode, and the first drain electrode,

wherein the second transistor comprises;

the second gate electrode;

the gate insulating layer provided over the second gate electrode;

a second oxide semiconductor layer provided over the gate insulating layer;

the second source electrode which is electrically connected to the second oxide semiconductor layer; and

the second drain electrode which is electrically connected to the second oxide semiconductor layer,

wherein the reduction prevention layer overlaps the second oxide semiconductor layer, the second source electrode, and the second drain electrode,

wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer contains indium, gallium, and zinc.

11. A logic circuit comprising:

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, wherein a first clock signal is input to the first gate electrode of the first transistor, and an input signal is input to the one of the first source electrode and the first drain electrode of the first transistor;

a first inverter comprising an input terminal and an output terminal, the input terminal of the first inverter electrically connected to the other of the first source electrode and the first drain electrode of the first transistor;

a second inverter comprising an input terminal and an output terminal, the input terminal of the second inverter electrically connected to the output terminal of the first inverter;

a third inverter comprising an input terminal electrically connected to the output terminal of the first inverter, and an output terminal outputting an output signal; and

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, wherein a second clock signal is input to the second gate electrode of the second transistor, one of the second source electrode and the second drain electrode of the second transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor, and the other of the second source electrode and the second drain electrode of the second transistor is electrically connected to the output terminal of the second inverter,

wherein each of the first inverter and the second inverter comprises;

a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode,

a fourth transistor comprising a fourth gate electrode, a fourth source electrode, and a fourth drain electrode,

a first terminal electrically connected to the fourth gate electrode of the fourth transistor; and

a second terminal electrically connected to a portion where the fourth transistor is connected to the third transistor,

wherein a high power supply voltage terminal is electrically connected to one of the third source electrode and the third drain electrode of the third transistor, and the third gate electrode of the third transistor is electrically connected to the other of the third source electrode and the third drain electrode of the third transistor;

wherein one of the fourth source electrode and the fourth drain electrode of the fourth transistor is electrically connected to the other of the third source electrode and the third drain electrode of the third transistor, and a low power supply voltage terminal is electrically connected to the other of the fourth source electrode and the fourth drain electrode of the fourth transistor,

wherein the third transistor comprises;

the third gate electrode;

a gate insulating layer provided over the third gate electrode;

a first oxide semiconductor layer provided over the gate insulating layer;

the third source electrode which is electrically connected to the first oxide semiconductor layer; and

the third drain electrode which is electrically connected to the first oxide semiconductor layer,

wherein a reduction prevention layer does not overlap the first oxide semiconductor layer, the third source electrode, and the third drain electrode,

wherein the fourth transistor comprises;

the fourth gate electrode;

the gate insulating layer provided over the fourth gate electrode;

a second oxide semiconductor layer provided over the gate insulating layer;

the fourth source electrode which is electrically connected to the first oxide semiconductor layer; and

the fourth drain electrode which is electrically connected to the first oxide semiconductor layer,

wherein the reduction prevention layer overlaps the second oxide semiconductor layer, the fourth source electrode, and the fourth drain electrode.

12. The logic circuit according to claim 11, wherein the fourth transistor comprises an oxygen vacancy control region between the fourth source electrode and the fourth drain electrode over a surface of the first oxide semiconductor layer, which is opposite to a surface in contact with the gate insulating layer.

13. The logic circuit according to claim 11, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer contains indium, gallium, and zinc.

14. The logic circuit according to claim 11, wherein the third transistor and the fourth transistor have the same conductivity type.

15. The logic circuit according to claim 11, wherein one of the fourth source electrode and the fourth drain electrode of the fourth transistor is in contact with the third gate electrode of the third transistor through an opening portion provided in the gate insulating layer.

16. The logic circuit according to claim 11,

wherein the third transistor does not include the reduction prevention layer over the first oxide semiconductor layer, the third source electrode, and the third drain electrode.

17. The logic circuit according to claim 11,

wherein the reduction prevention layer comprises one selected from the group of silicon oxide and aluminum oxide.

18. The logic circuit according to claim 11,

wherein the third transistor is a depletion transistor and the fourth transistor is an enhancement transistor.

19. The logic circuit according to claim 11,

wherein each of the third transistor and the fourth transistor further comprises a source region and a drain region in contact with part of the first oxide semiconductor layer, wherein the source region and the drain region are third oxide semiconductor layers.

20. The logic circuit according to claim 19,

wherein the third oxide semiconductor layers contain indium, gallium, and zinc.

21. A logic circuit comprising:

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode,

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode,

a first terminal electrically connected to the first gate electrode of the second transistor;

a second terminal electrically connected to a portion where the second transistor is connected to the first transistor,

wherein a high power supply voltage terminal is electrically connected to one of the first source electrode and the first drain electrode of the first transistor, and the first gate electrode of the first transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor;

wherein one of the second source electrode and the second drain electrode of the second transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor, and a low power supply voltage terminal is electrically connected to the other of the second source electrode and the second drain electrode of the second transistor,

wherein the first transistor comprises;

the first gate electrode;

a gate insulating layer provided over the first gate electrode;

a first oxide semiconductor layer provided over the gate insulating layer; and

the first source electrode and the first drain electrode in contact with part of the first oxide semiconductor layer,

wherein a reduction prevention layer does not overlap the first oxide semiconductor layer, the first source electrode, and the first drain electrode,

wherein the second transistor comprises;

the second gate electrode;

the gate insulating layer provided over the second gate electrode;

a second oxide semiconductor layer provided over the gate insulating layer; and

the second source electrode and the second drain electrode in contact with part of the second oxide semiconductor layer,

wherein the reduction prevention layer overlaps the second oxide semiconductor layer, the second source electrode, and the second drain electrode.

22. The logic circuit according to claim 21, wherein the second transistor comprises an oxygen vacancy control region between the second source electrode and the second drain electrode over a surface of the second oxide semiconductor layer, which is opposite to a surface in contact with the gate insulating layer.

23. The logic circuit according to claim 21, wherein the first transistor and the second transistor have the same conductivity type.

24. The logic circuit according to claim 21, wherein one of the second source electrode and the second drain electrode of the second transistor is in contact with the first gate electrode of the first transistor through an opening portion provided in the gate insulating layer.

25. The logic circuit according to claim 21,

wherein the first transistor does not include a reduction prevention layer over the first oxide semiconductor layer, the first source electrode, and the first drain electrode.

26. The logic circuit according to claim 21,

wherein the reduction prevention layer comprises one selected from the group of silicon oxide and aluminum oxide.

27. The logic circuit according to claim 21,

wherein the first transistor is a depletion transistor and the second transistor is an enhancement transistor.

28. A logic circuit comprising:

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode, wherein a first clock signal is input to the first gate electrode of the first transistor, and an input signal is input to the one of the first source electrode and the first drain electrode of the first transistor;

a first inverter comprising an input terminal and an output terminal, the input terminal of the first inverter electrically connected to the other of the first source electrode and the first drain electrode of the first transistor;

a second inverter comprising an input terminal and an output terminal, the input terminal of the second inverter electrically connected to the output terminal of the first inverter;

a third inverter comprising an input terminal electrically connected to the output terminal of the first inverter, and an output terminal outputting an output signal; and

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode, wherein a second clock signal is input to the second gate electrode of the second transistor, one of the second source electrode and the second drain electrode of the second transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor, and the other of the second source electrode and the second drain electrode of the second transistor is electrically connected to the output terminal of the second inverter,

wherein each of the first inverter and the second inverter comprises;

a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode,

a fourth transistor comprising a fourth gate electrode, a fourth source electrode, and a fourth drain electrode,

a first terminal electrically connected to the fourth gate electrode of the fourth transistor; and

a second terminal electrically connected to a portion where the fourth transistor is connected to the third transistor,

wherein a high power supply voltage terminal is electrically connected to one of the third source electrode and the third drain electrode of the third transistor, and the third gate electrode of the third transistor is electrically connected to the other of the third source electrode and the third drain electrode of the third transistor;

wherein one of the fourth source electrode and the fourth drain electrode of the fourth transistor is electrically connected to the other of the third source electrode and the third drain electrode of the third transistor, and a low power supply voltage terminal is electrically connected to the other of the fourth source electrode and the fourth drain electrode of the fourth transistor;

wherein the third transistor comprises;

the third gate electrode;

a gate insulating layer provided over the third gate electrode;

a first oxide semiconductor layer provided over the gate insulating layer; and

the third source electrode and the third drain electrode in contact with part of the first oxide semiconductor layer,

wherein a reduction prevention layer does not overlap the first oxide semiconductor layer, the third source electrode, and the third drain electrode,

wherein the fourth transistor comprises;

the fourth gate electrode;

the gate insulating layer provided over the fourth gate electrode;

a second oxide semiconductor layer provided over the gate insulating layer;

the fourth source electrode and the fourth drain electrode in contact with part of the second oxide semiconductor layer,

wherein the reduction prevention layer overlaps the second oxide semiconductor layer, the fourth source electrode, and the fourth drain electrode.

29. The logic circuit according to claim 28,

wherein the reduction prevention layer comprises one selected from the group of silicon oxide and aluminum oxide.

30. The logic circuit according to claim 28,

wherein the third transistor is a depletion transistor and the fourth transistor is an enhancement transistor.

32. The logic circuit according to claim 28,

wherein the third transistor does not include the reduction prevention layer over the first oxide semiconductor layer, the third source electrode, and the third drain electrode.

33. The logic circuit according to claim 28, wherein the fourth transistor comprises an oxygen vacancy control region between the fourth source electrode and the fourth drain electrode over a surface of the second oxide semiconductor layer, which is opposite to a surface in contact with the gate insulating layer.

34. The logic circuit according to claim 28, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer contains indium, gallium, and zinc.

35. The logic circuit according to claim 28, wherein the third transistor and the fourth transistor have the same conductivity type.

36. The logic circuit according to claim 28, wherein one of the fourth source electrode and the fourth drain electrode of the fourth transistor is in contact with the third gate electrode of the third transistor through an opening portion provided in the gate insulating layer.

31. A logic circuit comprising:

a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode,

a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode,

a first terminal electrically connected to the second gate electrode of the second transistor;

a second terminal electrically connected to a portion where the second transistor is connected to the first transistor,

wherein a high power supply voltage terminal is electrically connected to one of the first source electrode and the first drain electrode of the first transistor, and the first gate electrode of the first transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor;

wherein one of the second source electrode and the second drain electrode of the second transistor is electrically connected to the other of the first source electrode and the first drain electrode of the first transistor, and a low power supply voltage terminal is electrically connected to the other of the second source electrode and the second drain electrode of the second transistor,

wherein the first transistor comprises;

the first gate electrode;

a gate insulating layer provided over the first gate electrode;

a first oxide semiconductor layer provided over the gate insulating layer; and

the first source electrode and the first drain electrode in contact with part of the first oxide semiconductor layer,

wherein a reduction prevention layer does not overlap the first oxide semiconductor layer, the first source electrode, and the first drain electrode,

wherein the second transistor comprises;

the second gate electrode;

the gate insulating layer provided over the second gate electrode;

a second oxide semiconductor layer provided over the gate insulating layer; and

the second source electrode and the second drain electrode in contact with part of the second oxide semiconductor layer,

wherein the reduction prevention layer overlaps the second oxide semiconductor layer, the second source electrode, and the second drain electrode,

wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer contains indium, gallium, and zinc.