Power supply detection circuit

• US 8,373,446 B2
• Filed: 12/28/2010
• Issued: 02/12/2013
• Est. Priority Date: 12/28/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ali, Shahid, Manohar, Sujan Kundapur, Madan, Arvind
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US12/979,388
• Publication Number:
  US 20120161745A1
• Time in Patent Office: 777 Days
• Field of Search: 327 77- 81, 327/142, 327/143
• US Class Current: 327/77
• CPC Class Codes: H03K 17/223 in field-effect transistor switches

Abstract

Power supply detection circuit. The power supply detection circuit includes an input circuit responsive to a core power supply voltage to generate a first output voltage at a first node. The power supply detection circuit also includes a sense logic circuit to sense a voltage drop associated with the first output voltage, when the first output voltage is at a logic level HIGH. Further, the power supply detection circuit includes a current mirror circuit responsive to the voltage drop to increase voltage of the first output voltage to an input and output power supply voltage. Moreover, the power supply detection circuit also includes an output circuit that inverts the first output voltage to generate a second output voltage at a second node.

Claims

1. A power supply detection circuit comprising:

an input circuit responsive to a core power supply voltage to generate a first output voltage at a first node;

a sense logic circuit to sense a voltage drop associated with the first output voltage, when the first output voltage is at a logic level HIGH;

a current mirror circuit responsive to the voltage drop to increase voltage of the first output voltage to an input and output power supply voltage; and

an output circuit that inverts the first output voltage to generate a second output voltage at a second node;

wherein the input circuit comprises;

a first inverter to invert the core power supply voltage to generate the first output voltage; and

a first p-type metal oxide semiconductor (PMOS) transistor in series connection with the first inverter to enable increase of the first output voltage to the core power supply voltage;

wherein the sense logic circuit comprises;

a second PMOS transistor responsive to the first output voltage to sense the voltage drop associated with the first output voltage; and

a plurality of transistors, coupled to the second PMOS transistor, to enable sensing of the voltage drop;

wherein the current mirror circuit comprises;

a first n-type metal oxide semiconductor (NMOS) transistor, having a source coupled to the sense logic circuit, to control the current mirror circuit in response to the second output voltage;

a second NMOS transistor, having a gate coupled to the first node, to provide an input to the current mirror circuit in response to the first output voltage; and

a plurality of transistors, coupled to the first NMOS transistor and the second PMOS transistor, to increase the first output voltage to an input and output power supply voltage in response to the voltage drop.

2. The power supply detection circuit as claimed in claim 1, wherein the output circuit buffers the first output voltage if the first output voltage is at a logic level LOW.

3. The power supply detection circuit as claimed in claim 1, wherein the output circuit comprises:

a second inverter, coupled to the first node, to invert the first output voltage;

a third PMOS transistor, having a gate coupled to the second inverter, to generate the second output voltage; and

a third NMOS transistor, having a drain coupled to a drain of the third PMOS transistor, to enable generation of the second output voltage.

4. The power supply detection circuit as claimed in claim 1 and further comprising:

a MOS capacitor to charge the first node to the core power supply voltage;

a fourth PMOS transistor, having a source coupled to the first node and a drain coupled to a gate of the MOS capacitor, to charge the MOS capacitor; and

a pair of PMOS transistors in series connection with a gate of the fourth PMOS transistor, to enable charging of the MOS capacitor.