Power stage

• US 8,373,454 B2
• Filed: 07/01/2010
• Issued: 02/12/2013
• Est. Priority Date: 07/02/2009
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Acar, Mustafa, Nowak, Katarzyna
• Primary Examiner(s): JAGER, RYAN C
• Application Number:
  US12/829,250
• Publication Number:
  US 20110006814A1
• Time in Patent Office: 957 Days
• Field of Search: 327/108
• US Class Current: 327/112
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

An power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.

Claims

1. A driver circuit, comprising:

an output stage arranged between high and low voltage rails

at least one buffer stage having a high side buffer and a low side buffer wherein an output of a last buffer stage is connected to the output stage and an input of a first buffer stage is connected to an circuit input;

wherein the output stage is a differential output stage having a pair of high side differential inputs, a pair of low side differential inputs and a pair of differential stage outputs; and

in each buffer stage the high side buffer and the low side buffer are each differential buffers with a pair of differential inputs and a pair of differential outputs, each buffer stage being a self-biasing differential buffer stage, and

each of the high side buffers is implemented by transistors with an isolated well.

2. A circuit according to claim 1 wherein all transistors in the buffer stages are implemented with an isolated well.

3. A driver circuit according to claim 1 wherein each of the transistors implemented with an isolated well is implemented in triple-well CMOS.

4. A driver circuit according to claim 1, wherein in each buffer stage:

the outputs of the high side buffer are first and second differential outputs;

the outputs of the low side buffer are third and fourth differential outputs;

the inputs of the high side buffer are first and second differential inputs;

the inputs of the low side buffer are third and fourth differential inputs;

the high side buffer comprises a first p-type transistor and a first n-type transistor in series, with the first differential output between the first p-type transistor and the first n-type transistor and the gates of the first p-type transistor and the first n-type transistor connected to the first differential input;

a second p-type transistor and a second n-type transistor, in parallel with the first p-type transistor and the first n-type transistor, with the second differential output between the second p-type transistor and the second n-type transistor and the gates of the second p-type transistor and the second n-type transistor connected to the second differential input;

the low side buffer comprises a third p-type transistor and a third n-type transistor in series, with the third differential output between the third p-type transistor and the third n-type transistor and the gates of the third p-type transistor and the third n-type transistor connected to the third differential input; and

a fourth p-type transistor and a fourth n-type transistor, in parallel with the third p-type transistor and the third p-type transistor, with the fourth differential output between the fourth p-type transistor and the fourth n-type transistor and the gates of the fourth p-type transistor and the fourth n-type transistor connected to the fourth differential input.

5. A driver circuit according to claim 4, wherein the first and second p-type transistors have a source connected well and the first and second n-type transistors have a source connected well.

6. A driver circuit according to claim 1 having a plurality of buffer stages arranged in series, the output of each buffer stage except the last buffer stage being connected to the input of the next buffer stage.

7. A driver circuit according to claim 1 wherein

the circuit input is connected to one of the differential inputs of the low side buffer of the first buffer stage and to the other of the differential inputs of the low side buffer of the first buffer stage;

the circuit input is connected to the input of a level shift circuit; and

the output of the level shift circuit is connected to one of the differential inputs of the high side buffer of the first buffer stage and to the other of the differential inputs of the high side buffer of the first buffer stage.

8. A driver circuit according to claim 1 wherein the outputs of the output stage are connected through isolation capacitors to a transformer stage.

9. A driver circuit according to claim 1, further comprising

a plurality of capacitors for supplying an ac input signal to the inputs of the first buffer stage;

and

a resistive network between the high and low voltage rails for setting the dc voltage bias at the inputs of the first buffer stage.

10. A driver circuit according to claim 1 further comprising:

a high side phase shift circuit between one of the differential outputs of the high side buffer of the last buffer stage and one of the high side differential inputs of the output stage; and

a low side phase shift circuit between one of the differential outputs of the low side buffer of the last buffer stage and one of the low side differential inputs of the output stage;

wherein each of the outputs of the output stage is connected through a respective inductor to a dc drive node, the dc drive node being connected through a smoothing capacitor to the low side voltage rail so that the circuit acts as a voltage regulator outputting a regulated dc voltage on the dc drive node.