Output buffer circuit

• US 8,373,455 B1
• Filed: 01/25/2011
• Issued: 02/12/2013
• Est. Priority Date: 09/27/2006
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Li, Gabriel, McLaughlin, Alan
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/013,725
• Time in Patent Office: 749 Days
• Field of Search: 327108-112, 327/170
• US Class Current: 327/112
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

An output driver circuit can include at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node. A first variable current supply can generate a current having at least one component that is inversely proportional to a power supply voltage. A first driver switch element can be coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node.

Claims

1. An output driver circuit, comprising:

at least a first driver transistor having a source-drain path coupled between a first power supply node and an output node;

a first variable current supply that generates a current having at least one component that is inversely proportional to a power supply voltage; and

a first driver switch element coupled in series with the first variable current supply between a gate of the at least first driver transistor and a second power supply node, wherein the first driver switch and the first variable current supply are configured to control a rise time of the output driver circuit.

2. The output driver circuit of claim 1, wherein:

the at least first driver transistor includes a p-channel insulated gate field effect transistor, the first power supply node is a high power supply node and the second power supply node is a low power supply node.

3. The output driver circuit of claim 1, further including:

at least a second driver transistor having a source-drain path coupled between the second power supply node and the output node; and

a second variable current supply that generates a current having at least one component that is inversely proportional to the power supply voltage; and

a second driver switch element coupled in series with the second variable current supply between a gate of the at least second driver transistor and the first power supply node, wherein the second driver switch and the second variable current supply are configured to control a fall time of the output driver circuit.

4. The output driver circuit of claim 1, wherein:

the first variable current supply comprises a supply current source that provides source current to a reference current node, and a current mirror that shunts current away from the reference current node.

5. The output driver circuit of claim 4, wherein:

the current mirror includes an output mirror transistor having a source-drain path in series with the supply current source and in parallel with the reference current output node, a reference mirror transistor having a gate coupled to a gate of the output mirror transistor and to its drain, an impedance element coupled to the drain of the reference mirror transistor.

6. The output driver circuit of claim 1, wherein:

the first variable current supply includes a selectable current supply circuit that includes a current mirror having a reference current leg that receives a current having at least one component that is inversely proportional to the power supply voltage, a mirror current leg coupled to a selectable drive current node that mirrors the current flowing in the reference current leg, at least one first selectable mirror leg coupled to the selectable drive current node and coupled to mirror the current flowing in the reference current leg, and a mirror switch coupled in series with the at least one selectable mirror leg that is enabled in response to a drive signal.

14. The output driver circuit of claim 3, wherein:

the second driver transistor includes an n-channel insulated gate field effect transistor, and the first power supply node is a high power supply node and the second power supply node is a low power supply node.

7. An output driver circuit, comprising:

a first driver transistor that provides a low impedance path to an output node in response to a voltage at a first driver control node;

a first switch element coupled between the first driver control node and a first power supply node; and

a selectable current source coupled between the first driver control node and a second power supply node, the selectable current source generating a drive current that varies in response to a drive select value,

wherein the selectable current source includes a plurality of selectable current legs, each connected to a current control node and enabled to provide a current to the current control node in response to a corresponding drive control signal.

8. The output driver circuit of claim 7, wherein:

the selectable current source includes a drive current source circuit, and a first drive current switch element coupled in series with the current source circuit between the first driver control node and the second power supply node.

9. The output driver circuit of claim 7, wherein:

the selectable current source further includes a reference current source that provides a reference current having at least one component that is inversely proportional to a power supply voltage, and each of the selectable current legs provides a current proportional to the reference current.

10. The output driver circuit of claim 7, wherein:

the plurality of selectable current legs includes a drive current leg that provides a pre-drive current to a drive node, a drive strength modulator that selectively shunts current from the drive node in response to a drive strength control signal, and the drive current is proportional to the current at the drive node.

13. The output driver circuit of claim 7, further including:

a control logic circuit that selectively enables the first switch element and selectable current source in response to at least one input signal.

11. An output driver circuit, comprising:

a first driver transistor that provides a low impedance path to an output node in response to a voltage at a first driver control node;

a second driver transistor that provides a low impedance path to the output node in response to a voltage at a second driver control node; and

a first switch element coupled between the first driver control node and a first power supply node, and between the second driver control node and the first power supply node, the selectable current source generating a drive current that varies in response to a drive select value.

12. The output driver circuit of claim 11, further including:

a second switch element coupled between the second driver control node and the second power supply node.