Digital phase-locked loop architecture

• US 8,373,464 B2
• Filed: 04/07/2010
• Issued: 02/12/2013
• Est. Priority Date: 04/14/2009
• Status: Active Grant

• Current Assignee: Qualcomm technologies international, ltd. (Qualcomm, Inc.)
• Original Assignee: Cambridge Silicon Radio Limited (Qualcomm, Inc.)
• Inventors: Sornin, Nicolas
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US13/264,334
• Publication Number:
  US 20120105120A1
• Time in Patent Office: 1,042 Days
• Field of Search: 327/147, 327/156
• US Class Current: 327/156
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence

Abstract

A phase-locked loop circuit comprising: an oscillator (20) configured to generate an output signal; an input (25) for receiving a reference clock signal; a delay cell (26) configured to delay the reference clock signal to generate a delayed reference clock signal; a phase comparator (27) configured to generate a quantized signal indicative of the phase difference between the output signal and the delayed reference clock signal, an integrator (28) configured to integrate the quantized signal to form an integrated signal; a first feedback path (22) configured to control the phase and/or frequency of the oscillator in dependence on the integrated signal; and a second feedback path (23) configured to adjust the delay applied by the delay cell (26) in dependence on the integrated signal.

Claims

1. A phase-locked loop circuit comprising:

an oscillator configured to generate an output signal;

an input for receiving a reference clock signal;

a delay cell configured to delay the reference clock signal to generate a delayed reference clock signal;

a phase comparator configured to generate a quantised signal indicative of the phase difference between the output signal and the reference clock signal;

an integrator configured to integrate the quantised signal to form an integrated signal;

a first feedback path configured to control the phase and/or frequency of the oscillator in dependence on the integrated signal; and

a second feedback path configured to adjust the delay applied by the delay cell in dependence on the integrated signal.

2. A phase-locked loop as claimed in claim 1, wherein the first feedback path comprises a first low-pass filter configured to low-pass filter the integrated signal, the first feedback path being configured to control the phase and/or frequency of the oscillator in dependence on the output of the first low-pass filter.

3. A phase-locked loop as claimed in claim 2, wherein the first low-pass filter is implemented in the digital domain and the first feedback path comprises a first digital-to-analogue filter for converting the output of the first low-pass filter to the analogue domain, the first feedback path being configured to control the phase and/or frequency of the oscillator in dependence on the output of the first analogue to digital converter.

4. A phase-locked loop as claimed in claim 3, wherein the first feedback path comprises a second low-pass filter configured to low-pass filter in the analogue domain the output of the first digital-to-analogue converter, the first feedback path being configured to control the phase and/or frequency of the oscillator in dependence on the output of the second low-pass filter.

5. A phase-locked loop as claimed in any of claims 2 to 4, comprising a phase control input for receiving a first phase control signal, and wherein the first feedback path comprises means for combining with the output of the first low pass filter a first phase modulation command signal.

6. A phase-locked loop as claimed in any preceding claim, wherein the integrator is implemented in the digital domain.

7. A phase-locked loop as claimed in claim 6, wherein the integrator is an accumulator that is configured to accumulate the quantised signal to form an accumulated value, the instantaneous value of the integrated signal being the accumulated value.

8. A phase-locked loop as claimed in any preceding claim, wherein the second feedback path comprises means for combining with the output of the integrator one or both of a second phase modulation command signal and a frequency division signal.

9. A phase-locked loop as claimed in claim 8, comprising an input for receiving a frequency division command, and a second integrator configured to integrate the frequency division command to form the frequency division signal.

10. A phase-locked loop as claimed in any preceding claim, wherein the second feedback path comprises an amplifier for amplifying the integrated signal, the second feedback path being configured to control the delay applied by the delay cell in dependence on the output of the amplifier.

11. A phase-locked loop as claimed in claim 10, wherein the amplifier is a digital amplifier.

12. A phase-locked loop as claimed in any preceding claim, wherein the second feedback path comprises a second digital-to-analogue converter for converting a signal derived from the integrated signal to the analogue domain and the second feedback path is configured to control the delay applied by the delay cell in dependence on the output of the second digital-to-analogue converter.

13. A phase-locked loop as claimed in any preceding claim, wherein the phase comparator is a sampling device clocked by the delayed reference clock signal to sample the output signal.

14. A phase-locked loop as claimed in any of claims 1 to 12, wherein the phase comparator comprises:

a pulse comparator configured to generate a signal that is representative of the phase difference between the output signal and the reference clock signal;

an error-shaping circuit for error shaping the output of the pulse comparator; and

a sampling circuit clocked by the delayed reference clock signal to sample the error-shaped output of the pulse comparator.

15. A phase-locked loop as claimed in claim 14, wherein the pulse comparator configured to generate a signal whose current is representative of the phase difference between the output signal and the reference clock signal.

16. A phase-locked loop as claimed in claim 14 or 15, wherein the error-shaping circuit comprises:

a current source configured to add to the output of the pulse comparator a current dependent on the quantised signal; and

an integrator for integrating the signal at the output of the pulse comparator.

17. A phase-locked loop as claimed in claim 16, wherein the integrator for integrating the signal at the output of the pulse comparator is a capacitor connected between the output of the pulse comparator and a reference voltage.

18. A phase-locked loop as claimed in any of claims 14 to 17, wherein the sampling circuit comprises:

a comparator circuit for comparing the voltage at the output of the pulse comparator with first and second thresholds and for generating a quantised output having a first form if that voltage is below both the first and second thresholds, a second form if that voltage is between the first and second thresholds and a third form if that voltage is above both the first and second thresholds; and

a sampling device clocked by the delayed reference clock signal to sample the output of the comparator circuit.

19. A phase-locked loop as claimed in any preceding claim, wherein the integrator is implemented in the digital domain.

20. A phase-locked loop as claimed in any preceding claim, the phase-locked loop being implemented on a single integrated circuit.

21. A radio transmitter or receiver comprising a phase-locked loop as claimed in any preceding claim.