Nonvolatile semiconductor memory device

• US 8,374,033 B2
• Filed: 03/22/2010
• Issued: 02/12/2013
• Est. Priority Date: 07/06/2009
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kito, Masaru, Katsumata, Ryota, Kidoh, Masaru, Tanaka, Hiroyasu, Komori, Yosuke, Ishiduki, Megumi, Matsunami, Junya, Fujiwara, Tomoko, Aochi, Hideaki, Kirisawa, Ryouhei, Mikajiri, Yoshimasa, Oota, Shigeto, Fukuzumi, Yoshiaki
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US12/728,694
• Publication Number:
  US 20110002172A1
• Time in Patent Office: 1,058 Days
• Field of Search: 365/185.01, 365/185.18, 365/185.05, 365/185.26, 365/185.17, 365/185.14
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/3413 Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; a inner insulating film provided between the memory layer and the semiconductor pillar; a outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential.

Claims

1. A nonvolatile semiconductor memory device comprising:

a memory unit; and

a control unit,

the memory unit including;

a multilayer structure including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction;

a first semiconductor pillar piercing the multilayer structure in the first direction;

a first memory layer provided between the first semiconductor pillar and each of the electrode films;

a first inner insulating film provided between the first memory layer and the first semiconductor pillar;

a first outer insulating film provided between the first memory layer and each of the electrode films; and

a first wiring electrically connected to one end of the first semiconductor pillar, and

the control unit, in an operation of performing at least one of injection of a hole into the first memory layer and extraction of an electron from the first memory layer,

performing a first operation of setting the first wiring at a first potential and setting the electrode films at a second potential lower than the first potential, and

then performing a second operation of setting the first wiring at a third potential and setting the electrode films at a fourth potential higher than the third potential.

2. The device according to claim 1, wherein a difference between the fourth potential and the third potential is smaller than a difference between the first potential and the second potential.

3. The device according to claim 1, wherein the second potential is substantially equal to the third potential.

4. The device according to claim 1, wherein

the memory unit further includes a first selection gate electrode stacked on the multilayer structure in the first direction and pierced by the first semiconductor pillar on a side of the one end of the first semiconductor pillar, and

the control unit

sets the first selection gate electrode at a fifth potential lower than the first potential and higher than the second potential in a period of the first operation, and

sets the first selection gate electrode at a sixth potential higher than the third potential and lower than the fourth potential in a period of the second operation.

5. The device according to claim 4, wherein a difference between the sixth potential and the third potential is a voltage at which a first selection gate transistor formed at an intersection of the first selection gate electrode and the first semiconductor pillar is switched to an ON state.

6. The device according to claim 4, wherein,

in the first operation, the control unit

starts to change a potential of the first selection gate electrode from a potential lower than the fifth potential toward the fifth potential not prior to starting to change a potential of the first wiring from the third potential toward the first potential, and

after the starting to change the potential of the first selection gate electrode, finishes changing a potential of the first wiring from the first potential to the third potential not prior to finishing changing a potential of the first selection gate electrode from the fifth potential to the potential lower than the fifth potential.

7. The device according to claim 4, wherein,

in the second operation, the control unit

starts to change a potential of the electrode films from a potential lower than the fourth potential toward the fourth potential not prior to starting to change a potential of the first selection gate electrode from the second potential toward the sixth potential, and

after the starting to change the potential of the electrode films, finishes changing the potential of the first selection gate electrode from the sixth potential toward the potential lower than the fourth potential not prior to finishing changing the potential of the electrode films from the fourth potential toward the second potential.

8. The device according to claim 1, wherein

the memory unit further includes:

a second semiconductor pillar piercing the multilayer structure in the first direction;

a second memory layer provided between each of the electrode films and the second semiconductor pillar;

a second inner insulating film provided between the second memory layer and the second semiconductor pillar;

a second outer insulating film provided between each of the electrode films and the second memory layer;

a second wiring electrically connected to one end of the second semiconductor pillar; and

a connecting portion electrically connected to another end of the first semiconductor pillar and another end of the second semiconductor pillar, and

the control unit sets the second wiring at the first potential or sets the second wiring in a floating state in the first operation.

9. The device according to claim 8, wherein

the memory unit further includes a second selection gate electrode stacked on the multilayer structure in the first direction and pierced by the second semiconductor pillar on a side of the one end of the second semiconductor pillar, and

the control unit sets the second selection gate electrode at the fifth potential or sets the second selection gate electrode in a floating state in the first operation.